17
Preliminary User’s Manual U16035EJ1V0UM
LIST OF FIGURES (2/6)
Figure No.
Title
Page
5-8
System Clock and CPU Clock Switching .............................................................................................
103
6-1
Block Diagram of 16-Bit Timer/Event Counter 0 ..................................................................................
105
6-2
Format of 16-Bit Timer Mode Control Register 0 (TMC0) ....................................................................
109
6-3
Format of Capture/Compare Control Register 0 (CRC0) .....................................................................
110
6-4
Format of 16-Bit Timer Output Control Register 0 (TOC0) ..................................................................
111
6-5
Format of Prescaler Mode Register 0 (PRM0) .....................................................................................
112
6-6
Format of Port Mode Register 7 (PM7) ................................................................................................
113
6-7
Control Register Settings for Interval Timer Operation ........................................................................
114
6-8
Interval Timer Configuration Diagram ..................................................................................................
115
6-9
Timing of Interval Timer Operation .......................................................................................................
115
6-10
Control Register Settings for PPG Output Operation ...........................................................................
116
6-11
Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register ...................................................................................................................
117
6-12
Configuration Diagram for Pulse Width Measurement by Free-Running Counter ................................
118
6-13
Timing of Pulse Width Measurement Operation by Free-Running Counter
and One Capture Register (with Both Edges Specified) ......................................................................
118
6-14
Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter ............
119
6-15
CR01 Capture Operation with Rising Edge Specified ..........................................................................
120
6-16
Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified) .................................................................................................................
120
6-17
Control Register Settings for Pulse Width Measurement with
Free-Running Counter and Two Capture Registers .............................................................................
121
6-18
Timing of Pulse Width Measurement Operation by Free-Running Counter
and Two Capture Registers (with Rising Edge Specified) ....................................................................
122
6-19
Control Register Settings for Pulse Width Measurement by Means of Restart ...................................
123
6-20
Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) ..........
123
6-21
Control Register Settings in External Event Counter Mode .................................................................
124
6-22
External Event Counter Configuration Diagram ...................................................................................
125
6-23
External Event Counter Operation Timings (with Rising Edge Specified) ............................................
125
6-24
Control Register Settings in Square-Wave Output Mode .....................................................................
126
6-25
Square-Wave Output Operation Timing ...............................................................................................
127
6-26
16-Bit Timer Counter 0 (TM0) Start Timing ..........................................................................................
128
6-27
Timings After Change of Compare Register During Timer Count Operation .......................................
128
6-28
Capture Register Data Retention Timing .............................................................................................
129
6-29
Operation Timing of OVF0 Flag ...........................................................................................................
130
7-1
Block Diagram of 8-Bit Timer/Event Counter 50 ..................................................................................
133
7-2
Block Diagram of 8-Bit Timer/Event Counter 51 ..................................................................................
133
7-3
Format of Timer Clock Select Register 50 (TCL50) .............................................................................
135
7-4
Format of Timer Clock Select Register 51 (TCL51) .............................................................................
136
