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CHAPTER 8 WATCH TIMER
Preliminary User’s Manual U16035EJ1V0UM
Figure 8-3. Operation Timing of Watch Timer/Interval Timer
Caution When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control
register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first
interrupt request (INTWT) is generated after the register is set does not exactly match the
specification made with bit 3 (WTM3) of WTM. This is because there is a delay of one 9-bit
prescaler output cycle until the 5-bit counter starts counting. Subsequently, however, the INTWT
signal is generated at the specified intervals.
Remark
f
W
: Watch timer clock frequency
n: The number of times of interval timer operations
Figures in parentheses are for operation with f
W
= 32.768 kHz
0H
Start
Overflow
Overflow
5-bit counter
Count clock
f
W
/2
9
Watch timer
interrupt INTWT
Interval timer
interrupt INTWTI
Interrupt time of watch timer (0.5 s)
Interval time
(T)
T
Interrupt time of watch timer (0.5 s)
n x T
n x T
