196
CHAPTER 12 10-BIT A/D CONVERTER (
µ
PD780034AS SUBSERIES)
Preliminary User’s Manual U16035EJ1V0UM
Figure 12-2. Format of A/D Converter Mode Register 0 (ADM0)
Address: FF80H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
ADM0
ADCS0
TRG0
FR02
FR01
FR00
EGA01
EGA00
0
ADCS0
A/D conversion operation control
0
Stop conversion operation.
1
Enable conversion operation.
TRG0
Software start/hardware start selection
0
Software start
1
Hardware start
FR02
FR01
FR00
Conversion time selection
Note 1
0
0
0
144/f
X
(17.1
µ
s)
0
0
1
120/f
X
(14.3
µ
s)
0
1
0
96/f
X
(Setting prohibited
Note 2
)
1
0
0
72/f
X
(Setting prohibited
Note 2
)
1
0
1
60/f
X
(Setting prohibited
Note 2
)
1
1
0
48/f
X
(Setting prohibited
Note 2
)
Other than above
Setting prohibited
EGA01
EGA00
External trigger signal, edge specification
0
0
No edge detection
0
1
Falling edge detection
1
0
Rising edge detection
1
1
Both falling and rising edge detection
Notes 1.
Set so that the A/D conversion time is 14
µ
s or more.
2.
Setting prohibited because A/D conversion time is less than 14
µ
s.
Caution
When rewriting FR00 to FR02 to other than the same data, stop A/D conversion operations
once prior to performing rewrite.
Remarks 1.
f
X
: Main system clock oscillation frequency
2.
Figures in parentheses are for operation with f
X
= 8.38 MHz.
