NEC mPD780024AS Series Preliminary User'S Manual Download Page 294

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294

CHAPTER 19 INSTRUCTION SET

Preliminary User’s Manual U16035EJ1V0UM

Clock

Flag

Note 1

Note 2

Z AC CY

saddr.bit, $addr16

←

PC + 3 + jdisp8 if (saddr.bit) = 1

sfr.bit, $addr16

–

←

PC + 4 + jdisp8 if sfr.bit = 1

A.bit, $addr16

–

←

PC + 3 + jdisp8 if A.bit = 1

PSW.bit, $addr16

–

←

PC + 3 + jdisp8 if PSW.bit = 1

[HL].bit, $addr16

11 + n

←

PC + 3 + jdisp8 if (HL).bit = 1

saddr.bit, $addr16

←

PC + 4 + jdisp8 if (saddr.bit) = 0

sfr.bit, $addr16

–

←

PC + 4 + jdisp8 if sfr.bit = 0

A.bit, $addr16

–

←

PC + 3 + jdisp8 if A.bit = 0

PSW.bit, $addr16

–

←

PC + 4 + jdisp8 if PSW. bit = 0

[HL].bit, $addr16

11 + n

←

PC + 3 + jdisp8 if (HL).bit = 0

BTCLR

saddr.bit, $addr16

←

PC + 4 + jdisp8 if (saddr.bit) = 1

then reset (saddr.bit)

sfr.bit, $addr16

–

←

PC + 4 + jdisp8 if sfr.bit = 1

then reset sfr.bit

A.bit, $addr16

–

←

PC + 3 + jdisp8 if A.bit = 1

then reset A.bit

PSW.bit, $addr16

–

←

PC + 4 + jdisp8 if PSW.bit = 1

× × ×

then reset PSW.bit

[HL].bit, $addr16

12 + n + m

←

PC + 3 + jdisp8 if (HL).bit = 1

then reset (HL).bit

DBNZ

B, $addr16

–

←

B – 1, then

←

PC + 2 + jdisp8 if B

≠

C, $addr16

–

←

C –1, then

←

PC + 2 + jdisp8 if C

≠

saddr. $addr16

(saddr)

←

(saddr) – 1, then

←

PC + 3 + jdisp8 if(saddr)

≠

SEL

RBn

–

RBS1, 0

←

NOP

–

No Operation

–

←

1 (Enable Interrupt)

–

←

0 (Disable Interrupt)

HALT

–

Set HALT Mode

STOP

–

Set STOP Mode

Notes 1.

When the internal high-speed RAM area is accessed or instruction with no data access

When an area except the internal high-speed RAM area is accessed

Remarks 1.

One instruction clock cycle is one cycle of the CPU clock (f

CPU

) selected by the processor clock control

This clock cycle applies to internal ROM program.

n is the number of waits when external memory expansion area is read from.

m is the number of waits when external memory expansion area is written to.

Mnemonic

Operands

Byte

Operation

Instruction

Group

CPU

control

Condi-

tional

branch

Summary of Contents for mPD780024AS Series

Page 1: ...Chip Microcontrollers PD780021AS PD780022AS PD780023AS PD780024AS PD780031AS PD780032AS PD780033AS PD780034AS PD78F0034BS Document No U16035EJ1V0UM00 1st edition Date Published June 2002 N CP K Preli...

Page 2: ...2 Preliminary User s Manual U16035EJ1V0UM MEMO...

Page 3: ...erial All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Simil...

Page 4: ...plication examples The incorporation of these circuits software and information in the design of the customer s equipment shall be done under the full responsibility of the customer NEC Corporation as...

Page 5: ...9288 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Shanghai Ltd Shang...

Page 6: ...ctions Pin functions CPU functions Internal block functions Instruction set Interrupt Explanation of each instruction Other on chip peripheral functions How to Read This Manual It is assumed that the...

Page 7: ...e left and lower digits on the right Active low representation overscore over pin or signal name Note Footnote for item marked with Note in the text Caution Information requiring particular attention...

Page 8: ...ser s Manual U12326E 78K 0 Series Basic I Application Note U12704E Documents Related to Development Software Tools User s Manuals Document Name Document No RA78K0 Assembler Package Operation U14445E L...

Page 9: ...rammer User s Manual U13502E Other Related Documents Document Name Document No SEMICONDUCTOR SELECTION GUIDE Products Packages X13769E Semiconductor Device Mounting Technology Manual C10535E Quality G...

Page 10: ...rt 5 38 2 2 7 P70 to P75 Port 7 39 2 2 8 AVREF 39 2 2 9 AVDD 39 2 2 10 AVSS 39 3 2 11 RESET 39 2 2 12 X1 and X2 40 2 2 13 XT1 and XT2 40 2 2 14 VDD0 and VDD1 40 2 2 15 VSS0 and VSS1 40 2 2 16 VPP flas...

Page 11: ...0 75 4 2 2 Port 1 76 4 2 3 Port 2 77 4 2 4 Port 3 79 4 2 5 Port 4 81 4 2 6 Port 5 82 4 2 7 Port 7 83 4 3 Registers to Control Port Function 85 4 4 Operations of Port Function 89 4 4 1 Writing to I O p...

Page 12: ...Control 8 Bit Timer Event Counters 50 and 51 135 7 4 Operations of 8 Bit Timer Event Counters 50 and 51 140 7 4 1 Interval timer 8 bit operation 140 7 4 2 External event counter operation 144 7 4 3 S...

Page 13: ...UBSERIES 193 12 1 Functions of A D Converter 193 12 2 Configuration of A D Converter 194 12 3 Registers to Control A D Converter 195 12 4 Operations of A D Converter 198 12 4 1 Basic operations of A D...

Page 14: ...function control register 267 16 2 Operations of Standby Function 268 16 2 1 HALT mode 268 16 2 2 STOP mode 271 CHAPTER 17 RESET FUNCTION 274 17 1 Reset Function 274 CHAPTER 18 PD78F0034BS 278 18 1 M...

Page 15: ...16035EJ1V0UM B 2 Flash Memory Writing Tools 303 B 3 Debugging Tools 304 B 3 1 Hardware 304 B 3 2 Software 305 APPENDIX C EMBEDDED SOFTWARE 306 APPENDIX D REGISTER INDEX 307 D 1 Register Name Index 307...

Page 16: ...16 Configuration of General Purpose Register 58 4 1 Port Types 73 4 2 Block Diagram of P00 to P03 76 4 3 Block Diagram of P10 to P13 76 4 4 Block Diagram of P20 P22 P23 and P25 77 4 5 Block Diagram of...

Page 17: ...eration with Rising Edge Specified 120 6 16 Timing of Pulse Width Measurement Operation with Free Running Counter with Both Edges Specified 120 6 17 Control Register Settings for Pulse Width Measureme...

Page 18: ...gister WDTM 161 9 4 Format of Oscillation Stabilization Time Select Register OSTS 162 10 1 Block Diagram of Clock Output Buzzer Output Controller 165 10 2 Format of Clock Output Select Register CKS 16...

Page 19: ...Is Specified 201 12 8 A D Conversion by Software Start 202 12 9 Overall Error 203 12 10 Quantization Error 203 12 11 Zero Scale Offset 204 12 12 Full Scale Offset 204 12 13 Integral Linearity Error 20...

Page 20: ...5 6 Format of Memory Expansion Mode Register MEM 254 15 7 Format of Program Status Word 255 15 8 Non Maskable Interrupt Request Generation to Acknowledge Flowchart 257 15 9 Non Maskable Interrupt Requ...

Page 21: ...6 6 Figure No Title Page 18 4 Connection of Flashpro III in 3 Wire Serial I O Mode Using Handshake 282 18 5 Connection of Flashpro III in UART Mode 282 18 6 Connection of Flashpro III in Pseudo 3 Wire...

Page 22: ...Timer Event Counters 50 and 51 134 8 1 Interval Timer Interval Time 153 8 2 Configuration of Watch Timer 153 8 3 Interval Timer Interval Time 155 9 1 Watchdog Timer Program Loop Detection Time 158 9 2...

Page 23: ...t Servicing 262 16 1 HALT Mode Operating Status 268 16 2 Operation After HALT Mode Release 270 16 3 STOP Mode Operating Status 271 16 4 Operation After STOP Mode Release 273 17 1 Hardware Statuses Aft...

Page 24: ...peed 0 24 s 8 38 MHz operation with main system clock to ultra low speed 122 s 32 768 kHz operation with subsystem clock Instruction set suited to system control Bit manipulation possible in all addre...

Page 25: ...ic LQFP 10 10 Mask ROM PD780022ASGB 8ET 52 pin plastic LQFP 10 10 Mask ROM PD780023ASGB 8ET 52 pin plastic LQFP 10 10 Mask ROM PD780024ASGB 8ET 52 pin plastic LQFP 10 10 Mask ROM PD780031ASGB 8ET 52 p...

Page 26: ...74 PCL P73 TI51 TO51 P72 TI50 TO50 P71 TI01 52 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 34 33 32 31 30 29 28 27 P70 TI00 TO0 P03 INTP3 ADTRG P02 INTP2...

Page 27: ...Serial clock AVSS Analog ground SI30 SI31 Serial input BUZ Buzzer clock SO30 SO31 Serial output IC Internally connected TI00 TI01 TI50 TI51 Timer input INTP0 to INTP3 External interrupt input TO0 TO5...

Page 28: ...pin Products in mass production Products under development Y subseries products are compatible with I2 C bus ROMless version of the PD78078 100 pin 100 pin EMI noise reduced version of the PD78078 Inv...

Page 29: ...er PD780988 16 K to 60 K 3 ch Note 1 ch 8 ch 3 ch UART 2 ch 47 4 0 V control VFD PD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2 7 V drive PD780232 16 K to 24 K 3 ch 4 ch 40 4 5 V PD78044H 32...

Page 30: ...50 TO50 P72 TI51 TO51 P73 SI30 P20 SO30 P21 SCK30 P22 SI31 P34 SO31 P35 SCK31 P36 RxD0 P23 TxD0 P24 ASCK0 P25 AVDD AVSS AVREF BUZ P75 PCL P74 ANI0 P10 to ANI3 P13 INTP0 P00 to INTP3 P03 VDD0 VDD1 VSS0...

Page 31: ...t 4 CMOS I O 35 A D converter 8 bit resolution 4 channels PD780021AS 780022AS 780023AS 780024AS 10 bit resolution 4 channels PD780031AS 780032AS 780033AS 780034AS 78F0034BS Low voltage operation AVDD...

Page 32: ...imer 8 Bit Timer Watch Timer Watchdog Timer Event Counter Event Counter Operation Interval timer 1 channel 2 channels 1 channelNote 1 1 channelNote 2 mode External event counter Function Timer output...

Page 33: ...e driven directly Input output mode can be specified in 1 bit units An on chip pull up resistor can be used by software settings P70 I O Input TI00 TO0 P71 TI01 P72 TI50 TO50 P73 TI51 TO51 P74 PCL P75...

Page 34: ...TO50 TI51 External count clock input to 8 bit timer event counter 51 P73 TO51 TO0 Output 16 bit timer event counter 0 output Input P70 TI00 TO50 8 bit timer event counter 50 output Input P72 TI50 also...

Page 35: ...fter Reset Alternate Function VSS0 Ground potential for ports VSS1 Ground potential other than ports IC Internally connected Connect directly to VSS0 or VSS1 VPP High voltage application for program w...

Page 36: ...rnal interrupt request input and A D converter external trigger input a INTP0 to INTP3 INTP0 to INTP3 are external interrupt request input pins which can specify valid edges rising edge falling edge a...

Page 37: ...e serial data I O pins b SCK30 Serial interface serial clock I O pin c RXD0 and TXD0 Asynchronous serial interface serial data I O pins d ASCK0 Asynchronous serial interface serial clock input pin 2 2...

Page 38: ...se ports function as 8 bit I O ports They can be specified as input or output ports in 1 bit units with port mode register 4 PM4 On chip pull up resistors can be used by setting pull up resistor optio...

Page 39: ...ount clock input pin to 16 bit timer event counter and capture trigger signal input pin to 16 bit timer event counter capture register CR01 b TI01 Capture trigger signal input pin to 16 bit timer even...

Page 40: ...tential pin other than port pin 2 2 16 VPP flash memory versions only High voltage apply pin for flash memory programming mode setting and program write verify Connect directly to VSS0 or VSS1 in the...

Page 41: ...DD0 or VSS0 P20 SI30 8 C I O Input Independently connect to VDD0 or VSS0 via a P21 SO30 5 H resistor P22 SCK30 8 C Output Leave open P23 RxD0 P24 TxD0 5 H P25 ASCK0 8 C P34 SI31 8 C I O Input Independ...

Page 42: ...nput with hysteresis characteristics IN TYPE 8 C Data Output disable P ch IN OUT VDD0 N ch P ch VDD0 Pullup enable TYPE 5 H Data Output disable P ch IN OUT VDD0 N ch Input enable P ch VDD0 Pullup enab...

Page 43: ...g to each products indicated below PD780021AS 780031AS 42H PD780022AS 780032AS 44H PD780023AS 780033AS C6H PD780024AS 780034AS C8H PD78F0034BS Value for mask ROM version Figure 3 1 Memory Map PD780021...

Page 44: ...se registers 32 8 bits Internal ROM 16384 8 bits 3FFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF entry area CALLT table area Vector table area Program area Program area Program memor...

Page 45: ...se registers 32 8 bits Internal ROM 24576 8 bits 5FFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF entry area CALLT table area Vector table area Program area Program area Program memor...

Page 46: ...32768 8 bits 7FFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF entry area CALLT table area Vector table area Program area Program area Program memory space 8000H 7FFFH FEE0H FEDFH FF00...

Page 47: ...egisters 32 8 bits Flash memory 32768 8 bits 7FFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF entry area CALLT table area Vector table area Program area Program area Program memory sp...

Page 48: ...he 64 byte area 0000H to 003FH is reserved as a vector table area The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area O...

Page 49: ...E0H to FEFFH is allocated four general purpose register banks composed of eight 8 bit registers The internal high speed RAM can also be used as a stack memory 3 1 3 Special function register SFR area...

Page 50: ...and other considerations For areas containing data memory in particular special addressing methods designed for the functions of special function registers SFR and general purpose registers are avail...

Page 51: ...ers 32 8 bits Internal ROM 16384 8 bits 4000H 3FFFH FEE0H FEDFH FF00H FEFFH FFFFH Internal high speed RAM 512 8 bits Reserved FD00H FCFFH FF20H FF1FH FE20H FE1FH Special function registers SFRs 256 8...

Page 52: ...rs 32 8 bits Internal ROM 24576 8 bits 6000H 5FFFH FEE0H FEDFH FF00H FEFFH FFFFH Internal high speed RAM 1024 8 bits Reserved FB00H FAFFH FF20H FF1FH FE20H FE1FH Special function registers SFRs 256 8...

Page 53: ...rs 32 8 bits Internal ROM 32768 8 bits 8000H 7FFFH FEE0H FEDFH FF00H FEFFH FFFFH Internal high speed RAM 1024 8 bits Reserved FB00H FAFFH FF20H FF1FH FE20H FE1FH Special function registers SFRs 256 8...

Page 54: ...32 8 bits Flash memory 32768 8 bits 8000H 7FFFH FEE0H FEDFH FF00H FEFFH FFFFH Internal high speed RAM 1024 8 bits Reserved FB00H FAFFH FF20H FF1FH FE20H FE1FH Special function registers SFRs 256 8 bit...

Page 55: ...r of bytes of the instruction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H and 000...

Page 56: ...e operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases e In service priority flag ISP This flag manages the priority of acknowledgeable mask...

Page 57: ...PC15 to PC8 PC7 to PC0 Register pair lower SP SP 2 SP Register pair upper RET instruction POP rp instruction SP 1 PC7 to PC0 SP SP 2 SP SP 1 SP 2 SP SP 1 SP SP 3 Figure 3 13 Format of Stack Pointer 15...

Page 58: ...sts of 4 banks each bank consisting of eight 8 bit registers X A C B E D L and H Each register can also be used as an 8 bit register Two 8 bit registers can be used in pairs as a 16 bit register AX BC...

Page 59: ...he 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved with assembler for the 16 bit manipulation instru...

Page 60: ...R 00H FF13H 8 bit timer counter 51 TM51 FF16H A D conversion result register 0 ADCR0 FF17H FF18H Transmit shift register 0 TXS0 W FFH Receive buffer register 0 RXB0 R FF1AH Serial I O shift register...

Page 61: ...enerator control register 0 BRGC0 R W FFB0H Serial operation mode register 30 CSIM30 FFB8H Serial operation mode register 31 CSIM31 FFD0H External access areaNote 1 Undefined to FFDFH FFE0H Interrupt...

Page 62: ...ative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the pro...

Page 63: ...n the CALL addr16 or BR addr16 or CALLF addr11 instruction is executed CALL addr16 and BR addr16 instructions can be branched to the entire memory space The CALLF addr11 instruction is branched to the...

Page 64: ...nation address of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter PC and branched This function is carried out...

Page 65: ...ressing Instruction Register to Be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS...

Page 66: ...ction with the following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description...

Page 67: ...with immediate data in an instruction word becoming an operand address Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16...

Page 68: ...er event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at...

Page 69: ...n an instruction word This addressing is applied to the 240 byte spaces FF00H to FFCFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing Operand...

Page 70: ...k select flag RBS0 and RBS1 serve as an operand address for addressing the memory to be manipulated This addressing can be carried out for all the memory spaces Operand format Identifier Description D...

Page 71: ...gister bank specified with the register bank select flag RBS0 and RBS1 and the sum is used to address the memory Addition is performed by expanding the offset data as a positive number to 16 bits A ca...

Page 72: ...16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL B HL C Description example In the case of MOV A HL B...

Page 73: ...I O ports Figure 4 1 shows the port configuration Every port is capable of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can a...

Page 74: ...port Input output mode can be specified in 1 bit units An on chip pull up resistor can be used by software settings Port 3 3 bit I O port Input output mode can be specified in 1 bit units An on chip p...

Page 75: ...an specify the input mode output mode in 1 bit units with the port mode register 0 PM0 An on chip pull up resistor of P00 to P03 pins can be used for them in 1 bit units with a pull up resistor option...

Page 76: ...t 0 write signal 4 2 2 Port 1 Port 1 is an 4 bit input only port This port can also be used as an A D converter analog input Figure 4 3 shows a block diagram of port 1 Figure 4 3 Block Diagram of P10...

Page 77: ...esistor option register 2 PU2 This port has also alternate functions as serial interface data I O and clock I O RESET input sets port 2 to input mode Figures 4 4 and 4 5 show block diagrams of port 2...

Page 78: ...gure 4 5 Block Diagram of P21 and P24 RD P21 SO30 P24 TxD0 P ch WRPU WRPORT WRPM PU21 PU24 Output latch P21 P24 PM21 PM24 Selector VDD0 Internal bus Alternate function PU Pull up resistor option regis...

Page 79: ...port 3 Cautions 1 When reading port 3 using an 8 bit memory manipulation instruction do not use the lower 4 bits P33 to P30 because they are undefined When writing port 3 using an 8 bit memory manipu...

Page 80: ...16035EJ1V0UM Figure 4 7 Block Diagram of P35 RD P35 SO31 P ch WRPU WRPORT WRPM PU35 Output latch P35 PM35 Selector VDD0 Internal bus Alternate function PU Pull up resistor option register PM Port mode...

Page 81: ...de Figures 4 8 and 4 9 show a block diagram of port 4 and block diagram of the falling edge detector respectively Caution When using the falling edge detection interrupt INTKR be sure to set the memor...

Page 82: ...for them in 1 bit units with pull up resistor option register 5 PU5 Port 5 can drive LEDs directly RESET input sets port 5 to input mode Figure 4 10 shows a block diagram of port 5 Figure 4 10 Block...

Page 83: ...resistor option register 7 PU7 This port can also be used as a timer I O clock output and buzzer output RESET input sets port 7 to input mode Figures 4 11 and 4 12 show block diagrams of port 7 Figure...

Page 84: ...gure 4 12 Block Diagram of P74 and P75 RD P74 PCL P75 BUZ P ch WRPU WRPORT WRPM PU74 PU75 PM74 PM75 Selector VDD0 Alternate function Output latch P74 P75 Internal bus PU Pull up resistor option regist...

Page 85: ...PU2 to PU5 PU7 1 Port mode registers PM0 PM2 to PM5 PM7 These registers are used to set port input output in 1 bit units PM0 PM2 to PM5 and PM7 are independently set by a 1 bit or 8 bit memory manipu...

Page 86: ...e 1Note 1Note 1Note Address FF24H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 Address FF25H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM5 PM57 PM56 PM55 PM5...

Page 87: ...up resistors of the port pins corresponding to the bits in PU0 PU2 to PU5 and PU7 can be used PU0 PU2 to PU5 and PU7 are independently set by a 1 bit or 8 bit memory manipulation instruction RESET inp...

Page 88: ...20 Address FF33H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU3 0 PU36 PU35 PU34 0 0 0 0 Address FF34H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU4 PU47 PU46 PU45 PU44 PU43 PU42 PU41 PU40 Address FF...

Page 89: ...t pins the output latch contents for pins specified as input are undefined even for bits other than the manipulated bit 4 4 2 Reading from I O port 1 Output mode The output latch contents are read by...

Page 90: ...rocessor clock control register PCC 2 Subsystem clock oscillator The circuit oscillates at a frequency of 32 768 kHz Oscillation cannot be stopped If the subsystem clock oscillator is not used the int...

Page 91: ...lock oscillator fXT X1 X2 Main system clock oscillator fX Prescaler fX 2 fX 22 fX 23 fX 24 fXT 2 1 2 Prescaler Watch timer clock output function Clock to peripheral hardware CPU clock fCPU Standby con...

Page 92: ...ntrol register PCC The PCC sets whether to use CPU clock selection the ratio of division main system clock oscillator operation stop and subsystem clock oscillator internal feedback resistor The PCC i...

Page 93: ...23 1 0 0 fX 24 1 0 0 0 fXT 2 0 0 1 0 1 0 0 1 1 1 0 0 Other than above Setting prohibited Notes 1 Bit 5 is Read Only 2 When the CPU is operating on the subsystem clock MCC should be used to stop the m...

Page 94: ...clock oscillator oscillates with a crystal resonator or a ceramic resonator 8 38 MHz TYP connected to the X1 and X2 pins External clocks can be input to the main system clock oscillator In this case i...

Page 95: ...rnal clocks can be input to the subsystem clock oscillator In this case input a clock signal to the XT1 pin and an inverted phase clock signal to the XT2 pin Figure 5 5 shows an external circuit of th...

Page 96: ...ound point of the oscillator capacitor the same potential as VSS1 Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator Take speci...

Page 97: ...High current High current VSS1 VSS1 e Signals are fetched IC X2 X1 VSS1 Remark When using a subsystem clock replace X1 and X2 with XT1 and XT2 respectively Also insert resistors in series on the XT2 s...

Page 98: ...power consumption operations and clock operations connect the XT1 and XT2 pins as follows XT1 Connect to VDD0 XT2 Open In this state however some current may leak via the internal feedback resistor of...

Page 99: ...the main system clock selected two standby modes the STOP and HALT modes are available To reduce current consumption in the STOP mode the subsystem clock feedback resistor can be disconnected to stop...

Page 100: ...7 MCC of the PCC is set to 1 when operated with the main system clock the main system clock oscillation does not stop When bit 4 CSS of the PCC is set to 1 and the operation is switched to subsystem c...

Page 101: ...ctive of bits 0 to 2 PCC0 to PCC2 of the PCC b Watchdog timer counting stops Caution Do not execute the STOP instruction while the subsystem clock is in operation 5 6 Changing System Clock and CPU Clo...

Page 102: ...on 32 instructions 0 1 1 2 instructions 2 instructions 2 instructions 2 instructions fX 16fXT instruction 16 instructions 1 0 0 1 instruction 1 instruction 1 instruction 1 instruction fX 32fXT instruc...

Page 103: ...CPU starts executing the instruction at the minimum speed of the main system clock 3 81 s 8 38 MHz operation 2 After the lapse of a sufficient time for the VDD voltage to increase to enable operation...

Page 104: ...counter Square wave output 1 Interval timer TM0 generates interrupt request at the preset time interval 2 PPG output TM0 can output a square wave whose frequency and output pulse can be set freely 3 P...

Page 105: ...7 PM7 Note Note See Figure 4 11 Block Diagram of P70 to P73 and Figure 4 12 Block Diagram of P74 and P75 Figure 6 1 shows a block diagram Figure 6 1 Block Diagram of 16 Bit Timer Event Counter 0 Inter...

Page 106: ...erated if they match It can also be used as the register which holds the interval time when TM0 is set to interval timer operation When CR00 is used as a capture register It is possible to select the...

Page 107: ...alid edge of TI00 3 16 bit timer capture compare register 01 CR01 CR01 is a 16 bit register which has the functions of both a capture register and a compare register Whether it is used as a capture re...

Page 108: ...er 0 TOC0 Prescaler mode register 0 PRM0 Port mode register 7 PM7 1 16 bit timer mode control register 0 TMC0 This register sets the 16 bit timer operating mode the 16 bit timer counter 0 TM0 clear mo...

Page 109: ...nd CR00 match between TM0 and CR01 or TI00 valid edge OVF0 16 bit timer counter 0 TM0 overflow detection 0 Overflow not detected 1 Overflow detected Cautions 1 Timer operation must be stopped before w...

Page 110: ...capture register CRC01 CR00 capture trigger selection 0 Captures on valid edge of TI01 1 Captures on valid edge of TI00 by reverse phase CRC00 CR00 operating mode selection 0 Operates as compare regis...

Page 111: ...Control Register 0 TOC0 Address FF63H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 TOC0 0 0 0 TOC04 LVS0 LVR0 TOC01 TOE0 TOC04 Timer output F F control by match of CR01 and TM0 0 Inversion operation dis...

Page 112: ...1 TI00 valid edgeNote Note The external clock requires a pulse two times longer than internal clock fX 23 Cautions 1 If the valid edge of TI00 is to be set to the count clock do not set the clear star...

Page 113: ...r timer output set PM70 and the output latch of P70 to 0 PM7 is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets PM7 value to FFH Figure 6 6 Format of Port Mode Register 7 PM7...

Page 114: ...alue cleared to 0 and the interrupt request signal INTTM00 is generated Count clock of the 16 bit timer event counter can be selected with bits 0 and 1 PRM00 PRM01 of the prescaler mode register 0 PRM...

Page 115: ...OVF0 Clear circuit INTTM00 fX fX 22 fX 26 TI00 TO0 P70 Selector Noise eliminator fX 2 3 Figure 6 9 Timing of Interval Timer Operation Remark Interval time N 1 t N 0001H to FFFFH Count clock t TM0 cou...

Page 116: ...ter Settings for PPG Output Operation a 16 bit timer mode control register 0 TMC0 0 0 0 0 TMC03 1 TMC02 1 TMC01 0 OVF0 0 TMC0 Clears and starts on match between TM0 and CR00 b Capture compare control...

Page 117: ...of TM0 is taken into 16 bit timer capture compare register 01 CR01 and an external interrupt request signal INTTM01 is set Any of three edge can be selected rising falling or both edges specified by...

Page 118: ...it timer counter 0 TM0 OVF0 16 bit timer capture compare register 01 CR01 Internal bus INTTM01 Selector Figure 6 13 Timing of Pulse Width Measurement Operation by Free Running Counter and One Capture...

Page 119: ...0 is set Any of three edge can be selected rising falling or both edges as the valid edges for the TI00 TO0 P70 pin and the TI01 P71 pin specified by means of bits 4 and 5 ES00 and ES01 and bits 6 and...

Page 120: ...pecified Figure 6 16 Timing of Pulse Width Measurement Operation with Free Running Counter with Both Edges Specified t 0000H 0000H FFFFH 0001H D0 D0 TI01 pin input CR00 capture value INTTM01 INTTM00 O...

Page 121: ...00 and ES01 of prescaler mode register 0 PRM0 For TI00 TO0 P70 pin valid edge detection sampling is performed at the interval selected by means of the prescaler mode register 0 PRM0 and a capture oper...

Page 122: ...ngs in Figure 6 19 The edge specification can be selected from two types rising and falling edges by bits 4 and 5 ES00 and ES01 of the prescaler mode register 0 PRM0 In a valid edge detection the samp...

Page 123: ...ster 0 CRC0 0 0 0 0 0 CRC02 1 CRC01 1 CRC00 1 CRC0 CR00 as capture register Captures to CR00 at edge reverse to valid edge of TI00 TO0 P70 CR01 as capture register Remark 0 1 Setting 0 or 1 allows ano...

Page 124: ...e the falling edge or both edges can be selected with bits 4 and 5 ES00 and ES01 of prescaler mode register 0 PRM0 Because operation is carried out only after the valid edge is detected twice by sampl...

Page 125: ...Edge Specified TI00 pin input TM0 count value CR00 INTTM00 0000H 0001H 0002H 0003H 0004H 0005H N 1 N 0000H 0001H 0002H 0003H N Caution When reading the external event counter count value TM0 should b...

Page 126: ...ture compare control register 0 CRC0 0 0 0 0 0 CRC02 0 1 CRC01 0 1 CRC00 0 CRC0 CR00 as compare register c 16 bit timer output control register 0 TOC0 0 0 0 TOC04 0 LVS0 0 1 LVR0 0 1 TOC01 1 TOE0 1 TO...

Page 127: ...TIMER EVENT COUNTER 0 Preliminary User s Manual U16035EJ1V0UM Figure 6 25 Square Wave Output Operation Timing Count clock TM0 count value CR00 INTTM00 TO0 pin output 0000H 0001H 0002H N 1 N 0000H 0001...

Page 128: ...M0 and CR00 Set other than 0000H to 16 bit timer capture compare registers 00 01 CR00 CR01 This means 1 pulse count operation cannot be performed when it is used as the event counter 3 Operation after...

Page 129: ...is set upon detection of the valid edge Figure 6 28 Capture Register Data Retention Timing Count clock TM0 count value Edge input Interrupt request flag Capture read signal CR01 interrupt value N N 1...

Page 130: ...sabled 7 Contending operations 1 The contending operation between the read time of 16 bit timer capture compare register CR00 CR01 and capture trigger input CR00 CR01 used as capture register Capture...

Page 131: ...performed normally if that value is close to the timer value and larger than the timer value 2 Capture operation may not be performed for CR00 CR01 set in compare mode even if a capture trigger has be...

Page 132: ...t 1 Mode using 8 bit timer event counters alone single mode The timer operates as an 8 bit timer event counter It has the following functions Interval timer External event counter Square wave output P...

Page 133: ...ernal bus TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50 Invert level 8 bit timer mode control register 50 TMC50 S R S Q R INV Selector INTTM50 TO50 TI50 P72 Selector 8 bit timer counter 50 TM50 Selecto...

Page 134: ...ration and compare them in two times reading When count value is read during operation count clock input is temporary stopped and then the count value is read In the following situations count value i...

Page 135: ...mory manipulation instruction RESET input sets TCL5n to 00H Figure 7 3 Format of Timer Clock Select Register 50 TCL50 Address FF71H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 TCL50 0 0 0 0 0 TCL502 TC...

Page 136: ...7 to 0 Remarks 1 When cascade connection is used the settings of TCL5n0 to TCL5n2 n 0 1 are valid only for the lowermost timer 2 fX Main system clock oscillation frequency 3 Figures in parentheses ar...

Page 137: ...ating mode selection 0 Clear and start mode by matching between TM5n and CR5n 1 PWM free running mode TMC5n4 Single mode cascade connection mode selection 0 Single mode use the lowest timer 1 Cascade...

Page 138: ...This is because an interrupt may occur after TCE5n has been cleared Clear TCE5n to 0 using the following procedure TMMK5n 1 Mask set TCE5n 0 Timer clear TMIF5n 0 Interrupt request flag clear TMMK5n 0...

Page 139: ...TO51 pins for timer output set PM72 PM73 and output latches of P72 and P73 to 0 PM7 is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets PM7 to FFH Figure 7 6 Format of Port Mod...

Page 140: ...the interrupt request signals INTTM5n are generated The count clock of the TM5n can be selected with bits 0 to 2 TCL5n0 to TCL5n2 of the timer clock select register 5n TCL5n See 7 5 Cautions for 8 Bit...

Page 141: ...er Operation Timings 1 3 a Basic operation Remarks 1 Interval time N 1 t N 00H to FFH 2 n 0 1 t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n Start count Clear Clear 00H 01H N 00H 01H N 00H 01H...

Page 142: ...Interval Timer Operation Timings 2 3 b When CR5n 00H t Count clock TM5 CR5n TCE5n INTTM5n TO5n Interval time 00H 00H 00H 00H 00H c When CR5n FFH t Count clock TM5n CR5n TCE5n INTTM5n TO5n 01 FE FF 00...

Page 143: ...al Timer Operation Timings 3 3 d Operated by CR5n transition M N Count clock TM5 CR5n TCE5n INTTM5n TO5n 00H N N M N FFH 00H M 00H M CR5n transition TM5n overflows since M N H e Operated by CR5n trans...

Page 144: ...e timer clock select register 5n TCL5n is input Either the rising or falling edge can be selected When the TM5n counted values match the values of 8 bit timer compare register 5n CR5n TM5n is cleared...

Page 145: ...TCL5n Select count clock CR5n Compare value TMC5n Clear and start mode by match of TM5n and CR5n LVS5n LVR5n Timer Output F F Status Setting 1 0 High level output 0 1 Low level output Timer output F...

Page 146: ...sic operation Setting 1 Set port latch P72 P73 and port mode register 7 PM72 PM73 to 0 2 Set active level width with 8 bit timer compare register CR5n 3 Select count clock with timer clock select regi...

Page 147: ...01H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H N Active level Active level Inactive level b CR5n 0 c CR5n FFH n 0 1 Count clock TM5n CR5n TCE5n INTTM5n TO5n L Inactive level Inactive level 01H 00H FF...

Page 148: ...M N N 1 N 2 FFH 00H 01H M M 1 M 2 FFH 00H 01H 02H M M 1 M 2 N 02H M H b CR5n value transits from N to M after overflow of TM5n Count clock TM5n CR5n TCE5n INTTM5n TO5n N N 1 N 2 FFH 00H 01H N N 1 N 2...

Page 149: ...e clear start mode by match of TM50 and CR50 TM51 and CR51 TM50 TMC50 0000 0B don t care TM51 TMC51 0001 0B don t care 2 When TMC51 is set to TCE51 1 and then TMC50 is set to TCE50 1 count operation s...

Page 150: ...02H M 1 M 00H B 00H N M Interrupt request generation Level reverse Counter clear Operation stop 7 5 Cautions for 8 Bit Timer Event Counters 50 and 51 1 Timer start errors An error with the maximum of...

Page 151: ...ed it is necessary to restart the timer after changing CR5n Figure 7 14 Timing After Change of Compare Register During Timer Count Operation Count pulse CR5n TM5 count value N M X 1 X FFH 00H 01H 02H...

Page 152: ...mer The watch timer and the interval timer can be used simultaneously Figure 8 1 shows the watch timer block diagram Figure 8 1 Block Diagram of Watch Timer fX 27 fXT fW fW 24 fW 25 fW 26 fW 27 fW 28...

Page 153: ...rval Time When Operated at When Operated at When Operated at fX 8 38 MHz fX 4 19 MHz fXT 32 768 kHz 211 1 fX 24 1 fXT 244 s 489 s 488 s 212 1 fX 25 1 fXT 489 s 978 s 977 s 213 1 fX 26 1 fXT 978 s 1 96...

Page 154: ...WTM4 0 0 WTM1 WTM0 WTM7 Watch timer count clock selection 0 fX 27 65 4 kHz 1 fXT 32 768 kHz WTM6 WTM5 WTM4 Prescaler interval time selection 0 0 0 24 fW 0 0 1 25 fW 0 1 0 26 fW 0 1 1 27 fW 1 0 0 28 f...

Page 155: ...bit prescaler is not cleared Therefore an error up to 29 1 fW seconds occurs in the first overflow INTWT after zero second start Remark fX Main system clock oscillation frequency fXT Subsystem clock...

Page 156: ...he specification made with bit 3 WTM3 of WTM This is because there is a delay of one 9 bit prescaler output cycle until the 5 bit counter starts counting Subsequently however the INTWT signal is gener...

Page 157: ...DTM The watchdog timer and the interval timer cannot be used simultaneously Figure 9 1 shows a block diagram of the watchdog timer Figure 9 1 Block Diagram of Watchdog Timer fX 28 RUN Clock input cont...

Page 158: ...91 ms 216 1 fX 7 82 ms 217 1 fX 15 6 ms 218 1 fX 31 3 ms 220 1 fX 125 ms Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses are for operation with fX 8 38 MHz 2 Interval tim...

Page 159: ...Configuration Control registers Watchdog timer clock select register WDCS Watchdog timer mode register WDTM Oscillation stabilization time select register OSTS 9 3 Registers to Control Watchdog Timer...

Page 160: ...2 Format of Watchdog Timer Clock Select Register WDCS Address FF42H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 WDCS 0 0 0 0 0 WDCS2 WDCS1 WDCS0 WDCS2 WDCS1 WDCS0 Overflow time of watchdog timer interv...

Page 161: ...selectionNote 2 0 Interval timer modeNote 3 Maskable interrupt request occurs upon generation of an overflow 1 0 Watchdog timer mode 1 Non maskable interrupt request occurs upon generation of an over...

Page 162: ...eleasing the STOP mode by RESET input the time required to release is 217 fX Figure 9 4 Format of Oscillation Stabilization Time Select Register OSTS Address FFFAH After reset 04H R W Symbol 7 6 5 4 3...

Page 163: ...loop detection time is exceeded system reset or a non maskable interrupt request is generated according to WDTM bit 3 WDTM3 value The watchdog timer continues operating in the HALT mode but it stops i...

Page 164: ...mong maskable interrupts INTWDT has the highest priority at default The interval timer continues operating in the HALT mode but it stops in STOP mode Thus set RUN to 1 before the STOP mode is set clea...

Page 165: ...ed with the clock output select register CKS is output In addition the buzzer output is intended for square wave output of buzzer frequency selected with CKS Figure 10 1 shows the block diagram of clo...

Page 166: ...ter CKS Port mode register PM7 Note Note See Figure 4 12 Block Diagram of P74 and P75 10 3 Registers to Control Clock Output Buzzer Output Controller The following two types of registers are used to c...

Page 167: ...211 4 09 kHz 1 0 fX 212 2 04 kHz 1 1 fX 213 1 02 kHz CLOE PCL output enable disable specification 0 Stop clock division circuit operation PCL fixed to low level 1 Enable clock division circuit operat...

Page 168: ...the P75 BUZ pin for buzzer output set PM74 PM75 and the output latch of P74 P75 to 0 PM7 is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets PM7 to FFH Figure 10 3 Format of Po...

Page 169: ...utput controller is designed not to output pulses with a small width during output enable disable switching of the clock output As shown in Figure 10 4 be sure to start output from the low period of t...

Page 170: ...ecified 2 Software start Conversion is started by setting the A D converter mode register 0 ADM0 Select one channel for analog input from ANI0 to ANI3 to perform A D conversion In the case of hardware...

Page 171: ...al Interrupt Falling Edge Enable Register EGN ANI0 P10 ANI1 P11 ANI2 P12 ANI3 P13 Sample hold circuit Voltage comparator Successive approximation register SAR Controller Edge detector ADTRG INTP3 P03...

Page 172: ...2 A D conversion result register 0 ADCR0 The ADCR0 is an 8 bit register that stores the A D conversion result Each time A D conversion ends the conversion result is loaded from the successive approxi...

Page 173: ...on resolution When a digital pulse is applied to a pin adjacent to the pin in the process of A D conversion A D conversion values may not be obtained as expected due to coupling noise Thus do not appl...

Page 174: ...mode register 0 ADM0 Analog input channel specification register 0 ADS0 External interrupt rising edge enable register EGP External interrupt falling edge enable register EGN 1 A D converter mode regi...

Page 175: ...0 96 fX Setting prohibitedNote 2 1 0 0 72 fX Setting prohibitedNote 2 1 0 1 60 fX Setting prohibitedNote 2 1 1 0 48 fX Setting prohibitedNote 2 Other than above Setting prohibited EGA01 EGA00 Externa...

Page 176: ...3 Note Be sure to set bit 2 to 0 3 External interrupt rising edge enable register EGP external interrupt falling edge enable register EGN These registers specify the valid edge for INTP0 to INTP3 EGP...

Page 177: ...arator If the analog input is greater than 1 2 AVREF the MSB of SAR remains set If the analog input is smaller than 1 2 AVREF the MSB is reset 6 Next bit 6 of SAR is automatically set and the operatio...

Page 178: ...TAD0 Conversion result A D conversion operations are performed continuously until bit 7 ADCS0 of the A D converter mode register 0 ADM0 is reset 0 by software If a write operation is performed to the...

Page 179: ...NT VIN 256 0 5 AVREF or ADCR0 0 5 AVREF VIN ADCR0 0 5 AVREF 256 256 where INT Function which returns integer part of value in parentheses VIN Analog input voltage AVREF AVREF pin voltage ADCR0 A D con...

Page 180: ...f the voltage applied to the analog input pins specified by the analog input channel specification register 0 ADS0 starts Upon the end of the A D conversion the conversion result is stored in the A D...

Page 181: ...6035EJ1V0UM Figure 11 7 A D Conversion by Hardware Start When Falling Edge Is Specified A D conversion ADCR0 ADTRG INTAD0 ADM0 set ADCS0 1 TRG0 1 Standby state ANIn ANIn ANIn ANIm ANIm ANIm ANIn ANIn...

Page 182: ...INTAD0 is generated After one A D conversion operation is started and ended the next conversion operation is immediately started A D conversion operations are repeated until new data is written to AD...

Page 183: ...e and the theoretical value Zero scale offset full scale offset integral linearity error differential linearity error and errors which are combinations of these express overall error Furthermore quant...

Page 184: ...onversion characteristics deviate from the ideal linear relationship It expresses the maximum value of the difference between the actual measured value and the ideal straight line when the zero scale...

Page 185: ...me from when the analog input voltage was applied to the time when the digital output was obtained Sampling time is included in the conversion time in the characteristics table 9 Sampling time This is...

Page 186: ...t even if within the absolute maximum rating range the conversion value of that channel will be undefined and the conversion values of other channels may also be affected 3 Contending operations 1 Con...

Page 187: ...ANI0 to ANI3 5 ANI0 to ANI3 The analog input pins ANI0 to ANI3 also function as input port pins P10 to P13 When A D conversion is performed with any of pins ANI0 to ANI3 selected do not execute an in...

Page 188: ...re 11 17 A D Conversion End Interrupt Request Generation Timing ADM0 rewrite start of ANIn conversion A D conversion ADCR0 INTAD0 ANIn ANIn ANIm ANIm ANIn ANIn ANIm ANIm ADS0 rewrite start of ANIm con...

Page 189: ...iming of Reading Conversion Result When Conversion Result Is Normal 11 Notes on board design Locate analog circuits as far away from digital circuits as possible on the board because the analog circui...

Page 190: ...Capacitor for backup AVREF VDD0 AVSS AVDD VSS0 13 AVREF pin Connect a capacitor to the AVREF pin to minimize conversion errors due to noise If an A D conversion operation has been stopped and then is...

Page 191: ...acitance to the pins ANI0 to ANI3 An example of this is shown in Figure 11 23 In this case however the microcontroller cannot follow an analog signal with a high differential coefficient because a low...

Page 192: ...nary User s Manual U16035EJ1V0UM Figure 11 23 Example of Connection If Signal Source Impedance Is High C3 C2 R2 R1 Sensor internal circuit Microcontroller internal circuit R0 C0 0 1 F ANIn C1 C0 Lowpa...

Page 193: ...request INTAD0 is generated In the case of software start A D conversion is repeated Each time as A D conversion operation ends an interrupt request INTAD0 is generated Figure 12 1 Block Diagram of 1...

Page 194: ...n result register 0 ADCR0 The ADCR0 is a 16 bit register that stores the A D conversion results Lower 6 bits are fixed to 0 Each time A D conversion ends the conversion result is loaded from the succe...

Page 195: ...sion 7 AVREF pin This pin inputs the A D converter reference voltage It converts signals input to ANI0 to ANI3 into digital signals according to the voltage applied between AVREF and AVSS Caution A se...

Page 196: ...0 96 fX Setting prohibitedNote 2 1 0 0 72 fX Setting prohibitedNote 2 1 0 1 60 fX Setting prohibitedNote 2 1 1 0 48 fX Setting prohibitedNote 2 Other than above Setting prohibited EGA01 EGA00 Externa...

Page 197: ...I3 Note Be sure to set bit 2 to 0 3 External interrupt rising edge enable register EGP external interrupt falling edge enable register EGN These registers specify the valid edge for INTP0 to INTP3 EGP...

Page 198: ...arator If the analog input is greater than 1 2 AVREF the MSB of SAR remains set If the analog input is smaller than 1 2 AVREF the MSB is reset 6 Next bit 8 of SAR is automatically set and the operatio...

Page 199: ...onversion result A D conversion operations are performed continuously until bit 7 ADCS0 of the A D converter mode register 0 ADM0 is reset 0 by software If a write operation is performed to the ADM0 o...

Page 200: ...0 5 AVREF or ADCR0 0 5 AVREF VIN ADCR0 0 5 AVREF 1024 1024 where INT Function which returns integer part of value in parentheses VIN Analog input voltage AVREF AVREF pin voltage ADCR0 A D conversion...

Page 201: ...f the A D conversion the conversion result is stored in the A D conversion result register 0 ADCR0 and the interrupt request signal INTAD0 is generated After one A D conversion operation is started an...

Page 202: ...al INTAD0 is generated After one A D conversion operation is started and ended the next conversion operation is immediately started A D conversion operations are repeated until new data is written to...

Page 203: ...alue and the theoretical value Zero scale offset full scale offset integral linearity error differential linearity error and errors which are combinations of these express overall error Furthermore qu...

Page 204: ...l measured value of the analog input voltage and the theoretical value 3 2LSB when the digital output changes from 0 001 to 0 010 5 Full scale offset This shows the difference between the actual measu...

Page 205: ...sion time This expresses the time from when the analog input voltage was applied to the time when the digital output was obtained Sampling time is included in the conversion time in the characteristic...

Page 206: ...t even if within the absolute maximum rating range the conversion value of that channel will be undefined and the conversion values of other channels may also be affected 3 Contending operations 1 Con...

Page 207: ...pplied to a pin adjacent to the pin in the process of A D conversion the expected A D conversion value may not be obtainable due to coupling noise Therefore avoid applying pulses to pins adjacent to t...

Page 208: ...on start The first A D conversion value just after A D conversion operations start may not fall within the rating Polling A D conversion end interrupt request INTAD0 and take measures such as removing...

Page 209: ...eration To read the conversion result after stopping the A D conversion operation be sure to stop the A D conversion before the next conversion ends Figures 12 18 and 12 19 show the timing of reading...

Page 210: ...Capacitor for backup AVREF VDD0 AVSS AVDD VSS0 13 AVREF pin Connect a capacitor to the AVREF pinto minimize conversion errors due to noise If an A D conversion operation has been stopped and then is...

Page 211: ...acitance to the pins ANI0 to ANI3 An example of this is shown in Figure 12 23 In this case however the microcontroller cannot follow an analog signal with a high differential coefficient because a low...

Page 212: ...nary User s Manual U16035EJ1V0UM C3 C2 R2 R1 Sensor internal circuit Microcontroller internal circuit R0 C0 0 1 F ANIn C1 C0 Lowpass filter is created Output impedance of sensor Figure 12 23 Example o...

Page 213: ...x operation wherein one byte of data after the start bit is transmitted and received The on chip baud rate generator dedicated to UART enables communications using a wide range of selectable baud rate...

Page 214: ...TxD0 P24 PE0 FE0 OVE0 Asynchronous serial interface status register 0 ASIS0 INTSER0 INTST0 Baud rate generatorNote ASCK0 P25 fX 2 to fX 27 TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0 IRDAM0 Asynchronous serial...

Page 215: ...ned to TXS0 and the receive buffer register 0 RXB0 A read operation reads values from RXB0 2 Receive shift register 0 RX0 This register converts serial data input via the RxD0 pin to parallel data Whe...

Page 216: ...ol functions Asynchronous serial interface mode register 0 ASIM0 Asynchronous serial interface status register 0 ASIS0 Baud rate generator control register 0 BRGC0 1 Asynchronous serial interface mode...

Page 217: ...ection during reception parity errors do not occur 1 0 Odd parity 1 1 Even parity CL0 Character length specification 0 7 bits 1 8 bits SL0 Stop bit length specification for transmit data 0 1 bit 1 2 b...

Page 218: ...Stop bit not detected OVE0 Overrun error flag 0 No overrun error 1 Overrun errorNote 2 Next receive operation was completed before data was read from receive buffer register 0 RXB0 Notes 1 Even if a...

Page 219: ...0 0 0 fSCK 16 0 0 0 0 1 fSCK 17 1 0 0 1 0 fSCK 18 2 0 0 1 1 fSCK 19 3 0 1 0 0 fSCK 20 4 0 1 0 1 fSCK 21 5 0 1 1 0 fSCK 22 6 0 1 1 1 fSCK 23 7 1 0 0 0 fSCK 24 8 1 0 0 1 fSCK 25 9 1 0 1 0 fSCK 26 10 1...

Page 220: ...rface mode register 0 ASIM0 ASIM0 is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM0 to 00H Address FFA0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ASIM0 TXE0 RXE0 PS01...

Page 221: ...T mode settings are performed by the asynchronous serial interface mode register 0 ASIM0 asynchronous serial interface status register 0 ASIS0 and the baud rate generator control register 0 BRGC0 a As...

Page 222: ...do not occur 1 0 Odd parity 1 1 Even parity CL0 Character length specification 0 7 bits 1 8 bits SL0 Stop bit length specification for transmit data 0 1 bit 1 2 bits ISRM0 Receive completion interrup...

Page 223: ...aming error 1 Framing errorNote 1 Stop bit not detected OVE0 Overrun error flag 0 No overrun error 1 Overrun errorNote 2 Next receive operation was completed before data was read from receive buffer r...

Page 224: ...lection for baud rate generator k 0 0 0 0 fSCK 16 0 0 0 0 1 fSCK 17 1 0 0 1 0 fSCK 18 2 0 0 1 1 fSCK 19 3 0 1 0 0 fSCK 20 4 0 1 0 1 fSCK 21 5 0 1 1 0 fSCK 22 6 0 1 1 1 fSCK 23 7 1 0 0 0 fSCK 24 8 1 0...

Page 225: ...ock of the 5 bit counter substitute the input clock frequency to ASCK0 pin for fX in the above expression n Value set via TPS00 to TPS02 0 n 7 For details see Table 13 2 k Value set via MDL00 to MDL03...

Page 226: ...14 19200 3BH 1 10 3AH 0 16 38H 0 30H 1 73 2BH 1 14 31250 31H 1 3 30H 0 2DH 1 70 24H 0 21H 1 3 38400 2BH 1 10 2AH 0 16 28H 0 20H 1 73 1BH 1 14 76800 1BH 1 10 1AH 0 16 18H 0 10H 1 73 115200 12H 1 10 11H...

Page 227: ...13 6 Baud Rate Error Tolerance When k 0 Including Sampling Errors Basic timing clock cycle T START D0 D7 P STOP High speed clock clock cycle T enabling normal reception START D0 D7 P STOP Low speed c...

Page 228: ...or no parity Stop bit s 1 bit or 2 bits The asynchronous serial interface mode register 0 ASIM0 is used to set the character bit length parity selection and stop bit length within each data frame Whe...

Page 229: ...ceive data that include a parity bit and a parity error occurs when the counted result is an odd number ii Odd parity During transmission The number of bits in transmit data that includes a parity bit...

Page 230: ...ansmit completion interrupt request is shown in Figure 13 8 Figure 13 8 Timing of Asynchronous Serial Interface Transmit Completion Interrupt Request i Stop bit length 1 bit TxD0 output D0 D1 D2 D6 D7...

Page 231: ...e is completed the receive data in the shift register is transferred to the receive buffer register 0 RXB0 and a receive completion interrupt request INTSR0 occurs Even if an error has occurred the re...

Page 232: ...able 13 4 Causes of Receive Errors Receive Error Cause ASIS0 Value Parity error Parity specified during transmission does not match parity of receive data 04H Framing error Stop bit was not detected 0...

Page 233: ...tring of the UART frame which consists of pulses a start bit eight data bits and a stop bit The length of the electrical pulses that are used to transmit and receive in an IR frame is 3 16 the length...

Page 234: ...erance Pulse Width Minimum Value 3 16 Pulse Width Maximum Pulse Width Nominal Value kbits s of bit rate s Note 2 s s 115 2Note 1 0 87 1 41 1 63 2 71 Notes 1 At the operation time with fX 7 3728 MHz 2...

Page 235: ...ing UART output data UART Inverted data Infrared data transfer enable signal TxD0 pin output signal Start bit Stop bit Receive operation timing Data reception is delayed for one half of the specified...

Page 236: ...nd receive operations are enabled in 3 wire serial I O mode the processing time for data transfers is reduced The first bit of the serial transferred 8 bit data is fixed as the MSB 3 wire serial I O m...

Page 237: ...l transmit receive shift operations synchronized with the serial clock SIO3n is set by an 8 bit memory manipulation instruction When 1 is set to bit 7 CSIE3n of the serial operation mode register 3n C...

Page 238: ...nipulation instruction RESET input sets CSIM30 to 00H Caution In 3 wire serial I O mode set the port mode register PMXX as follows Set the output latch of the port set to output mode PMXX 0 to 0 When...

Page 239: ...mode Transfer start trigger SO30 output 0 Transmit transmit and receive mode Write to SIO30 Normal output 1 Receive only mode Read from SIO30 Fixed at low level SCL301 SCL300 Clock selection 0 0 Exter...

Page 240: ...3 wire serial I O mode set the port mode register PMXX as follows Set the output latch of the port set to output mode PMXX 0 to 0 When SIO31 is used During serial clock output PM36 0 Sets P36 SCK31 t...

Page 241: ...ode Transfer start trigger SO31 output 0 Transmit transmit and receive mode Write to SIO31 Normal output 1 Receive only mode Read from SIO31 Fixed at low level SCL311 SCL310 Clock selection 0 0 Extern...

Page 242: ...nstruction RESET input sets CSIM3n to 00H Address FFB0H SIO30 FFB8H SIO31 After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM3n CSIE3n 0 0 0 0 MODEn SCL3n1 SCL3n0 CSIE3n Enable disable specification for S...

Page 243: ...put latch of the port set to output mode PMXX 0 to 0 When SIO30 is used During serial clock output PM22 0 Sets P22 SCK30 to output mode master transmission or master reception P22 0 Sets output latch...

Page 244: ...r SO3n output 0 Transmit transmit and receive mode Write to SIO3n Normal output 1 Receive only mode Read from SIO3n Fixed at low level SCL3n1 SCL3n0 Clock selection 0 0 External clock input to SCK3n 0...

Page 245: ...0 1 3 Transfer start A serial transfer starts when the following two conditions have been satisfied and transfer data has been set or read to serial I O shift register 3n SIO3n SIO3n operation contro...

Page 246: ...registers PR0L PR0H PR1L Multiple high priority interrupts can be applied to low priority interrupts If two or more interrupts with the same priority are simultaneously generated each interrupt has a...

Page 247: ...H 9 INTCSI31 End of serial interface SIO3 SIO31 transfer 0016H 10 INTWTI Reference time interval signal from watch timer 001AH 11 INTTM00 Match between TM0 and CR00 001CH when CR00 is specified as com...

Page 248: ...t INTP0 to INTP3 Internal bus Interrupt request IF MK IE PR ISP Priority controller Vector table address generator Standby release signal External interrupt edge enable register EGP EGN Edge detector...

Page 249: ...upt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Priority specification flag MEM Memory expansion mode register IF MK IE PR ISP Internal bus Interrupt r...

Page 250: ...gs corresponding to interrupt request sources Table 15 2 Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Regist...

Page 251: ...3 2 1 0 IF0L STIF0 SRIF0 SERIF0 PIF3 PIF2 PIF1 PIF0 WDTIF Address FFE1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0H TMIF51 TMIF50 TMIF01 TMIF00 WTIIF 0 CSIIF31 CSIIF30 Address FFE2H After reset 00...

Page 252: ...SERMK0 PMK3 PMK2 PMK1 PMK0 WDTMK Address FFE5H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0H TMMK51 TMMK50 TMMK01 TMMK00 WTIMK 1 CSIMK31 CSIMK30 Address FFE6H After reset FFH R W Symbol 7 6 5 4 3 2...

Page 253: ...ets these registers to FFH Figure 15 4 Format of Priority Specification Flag Register PR0L PR0H PR1L Address FFE8H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0L STPR0 SRPR0 SERPR0 PPR3 PPR2 PPR1 PPR...

Page 254: ...fter reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGN 0 0 0 0 EGN3 EGN2 EGN1 EGN0 EGPn EGNn INTPn pin valid edge selection n 0 to 3 0 0 Interrupt disabled 0 1 Falling edge 1 0 Rising edge 1 1 Both rising and...

Page 255: ...a stack and the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag The...

Page 256: ...n maskable interrupt request generated during execution of a non maskable interrupt servicing program is acknowledged after the current execution of the non maskable interrupt servicing program is ter...

Page 257: ...4 1 with watchdog timer mode selected Overflow in WDT WDT interrupt servicing Interrupt control register not accessed Interval timer No Reset processing No Interrupt request generation Start of interr...

Page 258: ...n of NMI request 1 NMI request 2 held pending Servicing of NMI request 2 that was pended b If two non maskable interrupt requests are generated during non maskable interrupt servicing program executio...

Page 259: ...clocks When PR 1 8 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction the wait time becomes longer Remark 1 clock 1 fCPU fCPU CPU clock If two or more maskabl...

Page 260: ...uest held pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Vectored interrupt servicing Any high priority interrupt r...

Page 261: ...CPU clock Figure 15 13 Interrupt Request Acknowledge Timing Maximum Time Remark 1 clock 1 fCPU fCPU CPU clock 15 4 3 Software interrupt request acknowledge operation A software interrupt request is a...

Page 262: ...of the interrupt currently being serviced is generated during interrupt servicing it is not acknowledged for nesting Interrupt requests that are not enabled because of the interrupt disable state or...

Page 263: ...Main processing INTxx servicing INTyy servicing INTxx PR 0 INTyy PR 1 EI RETI IE 0 IE 0 EI 1 instruction execution RETI Interrupt request INTyy issued during servicing of interrupt INTxx is not acknow...

Page 264: ...INTxx EI instruction is not issued therefore interrupt request INTyy is not acknowledged and nesting does not take place The INTyy interrupt request is held pending and is acknowledged following exec...

Page 265: ...R0H and PR1L registers Caution The BRK instruction is not one of the above listed interrupt request hold instructions However the software interrupt activated by executing the BRK instruction causes t...

Page 266: ...ltra low current consumption Because this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time is required to secure an oscillati...

Page 267: ...bol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Selection of oscillation stabilization time 0 0 0 212 fX 488 s 0 0 1 214 fX 1 95 ms 0 1 0 215 fX 3 91 ms 0 1 1 216 fX 7 81 ms 1 0...

Page 268: ...ystem Item ClockNote 1 ClockNote 2 Clock Oscillation Clock Oscillation Stopped Clock generator Both main system clock and subsystem clock can be oscillated Clock supply to CPU stops CPU Operation stop...

Page 269: ...ase by Interrupt Request Generation HALT instruction Wait Wait Operation mode HALT mode Operation mode Oscillation Clock Standby release signal Interrupt request Remarks 1 The broken line indicates th...

Page 270: ...LT mode Operating mode Oscillation stop Clock RESET signal Oscillation Oscillation Reset period Remarks 1 fX Main system clock oscillation frequency 2 Values in parentheses are for operation with fX 8...

Page 271: ...he wait set using the oscillation stabilization time select register OSTS the operating mode is set The operating status in the STOP mode is described below Table 16 3 STOP Mode Operating Status STOP...

Page 272: ...lation stabilization time vectored interrupt service is carried out If interrupt acknowledge is disabled the next address instruction is executed Figure 16 4 STOP Mode Release by Interrupt Request Gen...

Page 273: ...s Operating mode STOP mode Operating mode Oscillation stop Clock RESET signal Oscillation Oscillation Reset period Remarks 1 fX Main system clock oscillation frequency 2 Values in parentheses are for...

Page 274: ...ion time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution starts after the lapse of oscillation stabilization time 217 fX The reset applied...

Page 275: ...of Reset Due to Watchdog Timer Overflow Hi Z Normal operation Reset period Oscillation stop Oscillation stabilization time wait Normal operation Reset processing X1 Watchdog timer overflow Internal re...

Page 276: ...registers CR00 CR01 Undefined Prescaler mode register PRM0 00H Mode control register TMC0 00H Output control register TOC0 00H 8 bit timer event counter Timer counters TM50 TM51 00H Compare registers...

Page 277: ...ronous serial interface mode register ASIM0 00H Asynchronous serial interface status register ASIS0 00H Baud rate generator control register BRGC0 00H Transmit shift register TXS0 FFH Receive buffer r...

Page 278: ...33AS 24 KB PD780023AS 24 KB PD780034AS 32 KB PD780024AS 32 KB Internal high speed RAM capacity 1024 bytesNote PD780031AS 512 bytes PD780021AS 512 bytes PD780032AS 512 bytes PD780022AS 512 bytes PD7800...

Page 279: ...ure 18 1 Format of Memory Size Switching Register IMS Address FFF0H After reset CFH R W Symbol 7 6 5 4 3 2 1 0 IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 Internal high speed RAM capacity...

Page 280: ...ble 18 3 Communication Mode List Communication Mode Number of Channels Pin UsedNote Number of VPP Pulses 3 wire serial I O 1 SI30 P20 0 SO30 P21 SCK30 P22 SI30 P20 3 SO30 P21 SCK30 P22 HS P25 3 wire s...

Page 281: ...ases the entire memory contents Batch blank check Checks the deletion status of the entire memory High speed write Performs writing to flash memory according to write start address and number of write...

Page 282: ...to 18 6 Figure 18 3 Connection of Flashpro III in 3 Wire Serial I O Mode VPP VDD RESET SCK SO SI GND VPP VDD RESET SCK3n SI3n SO3n VSS Flashpro III PD78F0034BS Figure 18 4 Connection of Flashpro III...

Page 283: ...User s Manual U16035EJ1V0UM Figure 18 6 Connection of Flashpro III in Pseudo 3 Wire Serial I O Mode VPP VDD RESET SCK SO SI GND VPP VDD RESET P72 Serial clock input P70 Serial data input P71 Serial da...

Page 284: ...CHAPTER 19 INSTRUCTION SET This chapter lists each instruction set of the PD780024AS 780034AS Subseries in table form For details of its operation and operation code refer to the separate document 78K...

Page 285: ...ames X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for specification Table 19 1 Operand Identifiers and Specification Methods Identifier Specification Me...

Page 286: ...ag AC Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register conten...

Page 287: ...C HL C A 1 6 7 m HL C A XCH A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 n m A addr16 A DE 1 4 6 n m A DE A HL 1 4 6 n m A HL A HL byte 2 8 10 n m A HL byte A HL B 2 8 10 n...

Page 288: ...CY A byte CY saddr byte 3 6 8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r A CY A saddr 2 4 5 A CY A saddr CY A addr16 3 8 9 n A CY A addr16 CY A HL 1 4 5 n A CY A HL CY A HL byte...

Page 289: ...A HL byte CY A HL B 2 8 9 n A CY A HL B CY A HL C 2 8 9 n A CY A HL C CY AND A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3 2 4 A A r r A 2 4 r r A A saddr 2 4 5 A A saddr A addr16 3...

Page 290: ...8 9 n A A HL B A HL C 2 8 9 n A A HL C CMP A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr A addr16 3 8 9 n A addr16 A HL 1 4 5 n A HL A HL byte 2 8...

Page 291: ...mulator after Subtract MOV1 CY saddr bit 3 6 7 CY saddr bit CY sfr bit 3 7 CY sfr bit CY A bit 2 4 CY A bit CY PSW bit 3 7 CY PSW bit CY HL bit 2 6 7 n CY HL bit saddr bit CY 3 6 8 saddr bit CY sfr bi...

Page 292: ...sfr bit 1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 HL bit 2 6 8 n m HL bit 1 CLR1 saddr bit 2 4 6 saddr bit 0 sfr bit 3 8 sfr bit 0 A bit 2 4 A bit 0 PSW bit 2 6 PSW bit 0 HL bit 2 6 8 n m HL bit 0 SET...

Page 293: ...SP SP 3 PUSH PSW 1 2 SP 1 PSW SP SP 1 rp 1 4 SP 1 rpH SP 2 rpL SP SP 2 POP PSW 1 2 PSW SP SP SP 1 R R R rp 1 4 rpH SP 1 rpL SP SP SP 2 MOVW SP word 4 10 SP word SP AX 2 8 SP AX AX SP 2 8 AX SP BR add...

Page 294: ...addr16 4 12 PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit HL bit addr16 3 10 12 n m PC PC 3 jdisp8 if HL bit 1 then reset HL bit DBNZ B addr16 2 6 B B 1 then PC PC 2 jdisp8 if B 0 C addr16 2 6 C C 1...

Page 295: ...RUCTION SET Preliminary User s Manual U16035EJ1V0UM 19 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4...

Page 296: ...H ROL SUB ADD ADD ADD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP...

Page 297: ...p MOVW MOVW addr16 MOVW SP MOVW MOVW Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand A bit sfr bit saddr bit PSW bit HL bit CY a...

Page 298: ...h instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand AX addr16 addr11 addr5 addr16 First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instr...

Page 299: ...10 bits 8 ch 8 bits 4 ch 10 bits 4 ch Internal 13 external 5 1 1 Time division method None Expansion up to F7FFH is possible Pull up resistor can be specified for P30 to P33 None 64 pin plastic SDIP 5...

Page 300: ...ure B 1 shows the development tool configuration Support for PC98 NX series Unless otherwise specified products compatible with IBM PC ATTM computers are compatible with PC98 NX series computers When...

Page 301: ...ile Embedded Software Real time OS Debugging Tool Assembler package C compiler package C library source file Device file Language Processing Software Flash memory write adapter In circuit Emulator Pow...

Page 302: ...indows however by using the Project Manager included in assembler package on Windows Part number S RA78K0 This compiler converts programs written in C language into object codes executable with a micr...

Page 303: ...F780024 S DF780034 S CC78K0 L Host machine OS Supply medium AB13 PC 9800 Series Windows Japanese version 3 5 inch 2HD FD BB13 IBM PC AT or compatibles Windows English version 3P16 HP9000 Series 700 HP...

Page 304: ...e adapter which is required to connect this emulator to the host machine This board is connected to the IE 78K0 NS to expand its functions Adding this board adds a coverage function and enhances debug...

Page 305: ...ardware development without having to use an in circuit emulator thereby providing higher development efficiency and software quality The SM78K0 should be used in combination with the optional device...

Page 306: ...indows Part number S RX78013 Caution When purchasing the RX78K0 fill in the purchase application form in advance and sign the user agreement Remark and in the part number differ depending on the host...

Page 307: ...pare register 51 CR51 134 8 bit timer counter 50 TM50 135 8 bit timer counter 51 TM51 135 8 bit timer mode control register 50 TMC50 136 8 bit timer mode control register 51 TMC51 136 External interru...

Page 308: ...on register 3 PU3 87 Pull up resistor option register 4 PU4 87 Pull up resistor option register 5 PU5 87 Pull up resistor option register 7 PU7 87 R Receive buffer register 0 RXB0 215 Receive shift re...

Page 309: ...134 CR51 8 bit timer compare register 51 134 CRC0 Capture compare control register 0 110 CSIM30 Serial operation mode register 30 238 CSIM31 Serial operation mode register 31 240 E EGN External inter...

Page 310: ...on register 3 87 PU4 Pull up resistor option register 4 87 PU5 Pull up resistor option register 5 87 PU7 Pull up resistor option register 7 87 R RXB0 Receive buffer register 0 215 RX0 Receive shift re...

Page 311: ...ax 86 21 6841 1137 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Market Communication Dept Fax 49 211 650...

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