NEC mPD780024AS Series, Preliminary User'S Manual

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Preliminary User’s Manual U16035EJ1V0UM
LIST OF FIGURES (3/6)
Figure No. Title Page
7-5 Format of 8-Bit Timer Mode Control Register 5n (TMC5n) .................................................................. 137
7-6 Format of Port Mode Register 7 (PM7) ................................................................................................ 139
7-7 Interval Timer Operation Timings ......................................................................................................... 141
7-8 External Event Counter Operation Timing (with Rising Edge Specified) ............................................. 144
7-9 Square-Wave Output Operation Timing ............................................................................................... 145
7-10 PWM Output Operation Timing ............................................................................................................ 147
7-11 Timing of Operation by CR5n Transition .............................................................................................. 148
7-12 16-Bit Resolution Cascade Connection Mode ..................................................................................... 150
7-13 8-Bit Timer Counter Start Timing ......................................................................................................... 150
7-14 Timing After Change of Compare Register During Timer Count Operation ......................................... 151
8-1 Block Diagram of Watch Timer ............................................................................................................. 152
8-2 Format of Watch Timer Operation Mode Register (WTM) ................................................................... 154
8-3 Operation Timing of Watch Timer/Interval Timer .................................................................................. 156
9-1 Block Diagram of Watchdog Timer ....................................................................................................... 157
9-2 Format of Watchdog Timer Clock Select Register (WDCS) ................................................................. 160
9-3 Format of Watchdog Timer Mode Register (WDTM) ............................................................................ 161
9-4 Format of Oscillation Stabilization Time Select Register (OSTS) ........................................................ 162
10-1 Block Diagram of Clock Output/Buzzer Output Controller ................................................................... 165
10-2 Format of Clock Output Select Register (CKS) .................................................................................... 167
10-3 Format of Port Mode Register 7 (PM7) ................................................................................................ 168
10-4 Remote Control Output Application Example ...................................................................................... 169
11-1 Block Diagram of 8-Bit A/D Converter ................................................................................................. 171
11-2 Format of A/D Converter Mode Register 0 (ADM0) ............................................................................. 175
11-3 Format of Analog Input Channel Specification Register 0 (ADS0) ...................................................... 176
11-4 Format of External Interrupt Rising Edge Enable Register (EGP) and
External Interrupt Falling Edge Enable Register (EGN) ....................................................................... 176
11-5 Basic Operation of 8-Bit A/D Converter ............................................................................................... 178
11-6 Relationship Between Analog Input Voltage and A/D Conversion Result ............................................ 179
11-7 A/D Conversion by Hardware Start (When Falling Edge Is Specified) ................................................. 181
11-8 A/D Conversion by Software Start ....................................................................................................... 182
11-9 Overall Error ......................................................................................................................................... 183
11-10 Quantization Error ................................................................................................................................ 183
11-11 Zero Scale Offset ................................................................................................................................. 184
11-12 Full Scale Offset ................................................................................................................................... 184
11-13 Integral Linearity Error ......................................................................................................................... 184
11-14 Differential Linearity Error .................................................................................................................... 184
11-15 Example of Method of Reducing Current Consumption in Standby Mode ........................................... 186