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CHAPTER 5 CLOCK GENERATOR
Preliminary User’s Manual U16035EJ1V0UM
Figure 5-1. Block Diagram of Clock Generator
FRC
Subsystem
clock
oscillator
f
XT
X1
X2
Main system
clock
oscillator
f
X
Prescaler
f
X
2
f
X
2
2
f
X
2
3
f
X
2
4
f
XT
2
1/2
Prescaler
Watch timer,
clock output
function
Clock to
peripheral
hardware
CPU clock
(f
CPU
)
Standby
controller
Wait
controller
3
STOP
MCC FRC
CLS
CSS PCC2 PCC1 PCC0
Processor clock control register
(PCC)
Internal bus
Selector
XT1
XT2
