131
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0
Preliminary User’s Manual U16035EJ1V0UM
(9) Capture operation
<1>
If TI00 is specified as the valid edge of the count clock, capture operation by the capture register specified
as the trigger for TI00 is not possible.
<2>
If both the rising and falling edges are selected as the valid edges of TI00, capture is not performed.
<3>
To ensure the reliability of the capture operation, the capture trigger requires a pulse two times longer than
the count clock selected by prescaler mode register 0 (PRM0).
<4>
The capture operation is performed at the fall of the count clock. An interrupt request input (INTTM0n),
however, is generated at the rise of the next count clock.
(10) Compare operation
<1>
When the 16-bit timer capture/compare register (CR00/CR01) is overwritten during timer operation, match
interrupt may be generated or clear operation may not be performed normally if that value is close to the
timer value and larger than the timer value.
<2>
Capture operation may not be performed for CR00/CR01 set in compare mode even if a capture trigger
has been input.
(11) Edge detection
<1>
If the TI00 pin or the TI01 pin is high level immediately after system reset and rising edge or both the rising
and falling edges are specified as the valid edge for the TI00 pin or TI01 pin to enable the 16-bit timer counter
0 (TM0) operation, a rising edge is detected immediately after. Be careful when pulling up the TI00 pin or
the TI01 pin. However, the rising edge is not detected at restart after the operation has been stopped once.
<2>
The sampling clock used to eliminate noise differs when a TI00 valid edge is used as count clock and when
it is used as a capture trigger. In the former case, the count clock is f
X
/2
3
, and in the latter case the count
clock is selected by prescaler mode register 0 (PRM0). When a valid edge is detected twice by sampling,
the capture operation is started, therefore noise with short pulse widths can be eliminated.
