148
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Preliminary User’s Manual U16035EJ1V0UM
(2) Operated by CR5n transition
Figure 7-11. Timing of Operation by CR5n Transition
(a) CR5n value transits from N to M before overflow of TM5n
Count clock
TM5n
CR5n
TCE5n
INTTM5n
TO5n
CR5n transition (N
→
M)
N N+1 N+2
FFH 00H 01H
M M+1 M+2
FFH 00H 01H 02H
M M+1 M+2
N
02H
M
H
(b) CR5n value transits from N to M after overflow of TM5n
Count clock
TM5n
CR5n
TCE5n
INTTM5n
TO5n
N
N+1 N+2
FFH 00H 01H
N
N+1 N+2
FFH 00H 01H 02H
N
02H
N
H
03H
M
M M+1 M+2
CR5n transition (N
→
M)
(c) CR5n value transits from N to M between two clocks (00H and 01H) after overflow of TM5n
Count clock
TM5n
CR5n
TCE5n
INTTM5n
TO5n
N
N+1 N+2
FFH 00H 01H
N
N+1 N+2
FFH 00H 01H 02H
N
02H
N
H
M
M M+1 M+2
CR5n transition (N
→
M)
n = 0, 1
