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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0
Preliminary User’s Manual U16035EJ1V0UM
6.5 Cautions for 16-Bit Timer/Event Counter 0
(1) Timer start errors
An error with a maximum of one clock may occur concerning the time required for a match signal to be generated
after timer start. This is because the 16-bit timer counter 0 (TM0) is started asynchronously with the count clock.
Figure 6-26. 16-Bit Timer Counter 0 (TM0) Start Timing
TM0 count value
0000H
0001H
0002H
0004H
Count clock
Timer start
0003H
(2) 16-bit timer compare register setting (in clear & start mode on match between TM0 and CR00)
Set other than 0000H to 16-bit timer capture/compare registers 00, 01 (CR00, CR01). This means 1-pulse count
operation cannot be performed when it is used as the event counter.
(3) Operation after compare register change during timer count operation
If the value after the 16-bit timer capture/compare register 00 (CR00) is changed is smaller than that of 16-bit
timer counter 0 (TM0), TM0 continues counting, overflows and then restarts counting from 0. Thus, if the value
(M) after CR00 is changed is smaller than the value (N) before it was changed, it is necessary to reset and restart
the timer after changing CR00.
Figure 6-27. Timings After Change of Compare Register During Timer Count Operation
CR00
N
M
Count clock
TM0 count value
X – 1
X
FFFFH
0000H
0001H
0002H
Remark
N > X > M
