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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0
Preliminary User’s Manual U16035EJ1V0UM
CR00 is set by a 16-bit memory manipulation instruction.
After RESET input, the value of CR00 is undefined.
Cautions 1. Set a value other than 0000H in CR00 in the clear & start mode on match between TM0 and
CR00. However, in the free-running mode and in the clear mode using the valid edge of
TI00, if 0000H is set to CR00, an interrupt request (INTTM00) is generated following overflow
(FFFFH).
2. If the value after CR00 is changed is smaller than that of 16-bit timer counter 0 (TM0), TM0
continues counting, overflows and then restarts counting from 0. Thus, if the value after
CR00 is changed is smaller than the value before it was changed, it is necessary to restart
the timer after changing CR00.
3. When P70 is used as the valid edge of TI00, it cannot be used as timer output (TO0).
Moreover, when P70 is used as TO0, it cannot be used as the valid edge of TI00.
(3) 16-bit timer capture/compare register 01 (CR01)
CR01 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is
used as a capture register or a compare register is set by bit 2 (CRC02) of capture/compare control register 0 (CRC0).
•
When CR01 is used as a compare register
The value set in the CR01 is constantly compared with the 16-bit timer counter 0 (TM0) count value, and an
interrupt request (INTTM01) is generated if they match.
•
When CR01 is used as a capture register
It is possible to select the valid edge of the TI00/TO0/P70 pin as the capture trigger. The TI00/TO0/P70 valid
edge is set by means of prescaler mode register 0 (PRM0).
CR01 is set by a 16-bit memory manipulation instruction.
After RESET input, the value of CR01 is undefined.
Caution
Set other than 0000H to CR01. This means 1-pulse count operation cannot be performed when
CR01 is used as the event counter. However, in the free-running mode and in the clear mode
using the valid edge of TI00, if 0000H is set to CR01, an interrupt request (INTTM01) is
generated following overflow (FFFFH).
