NEC mPD780024AS Series, Preliminary User'S Manual

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Preliminary User’s Manual U16035EJ1V0UM
CONTENTS
CHAPTER 1 OUTLINE ....................................................................................................................... 24
1.1 Features .................................................................................................................................... 24
1.2 Applications ............................................................................................................................. 25
1.3 Ordering Information ............................................................................................................... 25
1.4 Pin Configuration (Top View) ................................................................................................. 26
1.5 78K/0 Series Lineup ................................................................................................................. 28
1.6 Block Diagram .......................................................................................................................... 30
1.7 Outline of Function .................................................................................................................. 31
CHAPTER 2 PIN FUNCTION ............................................................................................................ 33
2.1 Pin Function List ...................................................................................................................... 33
2.2 Description of Pin Functions .................................................................................................. 36
2.2.1 P00 to P03 (Port 0) ........................................................................................................................ 36
2.2.2 P10 to P13 (Port 1) ........................................................................................................................ 36
2.2.3 P20 to P25 (Port 2) ........................................................................................................................ 37
2.2.4 P34 to P36 (Port 3) ........................................................................................................................ 37
2.2.5 P40 to P47 (Port 4) ........................................................................................................................ 38
2.2.6 P50 to P57 (Port 5) ........................................................................................................................ 38
2.2.7 P70 to P75 (Port 7) ........................................................................................................................ 39
2.2.8 AV
REF
............................................................................................................................................. 39
2.2.9 AV
DD
.............................................................................................................................................. 39
2.2.10 AV
SS
............................................................................................................................................. 39
3.2.11 RESET ........................................................................................................................................ 39
2.2.12 X1 and X2 ................................................................................................................................... 40
2.2.13 XT1 and XT2 ............................................................................................................................... 40
2.2.14 V
DD0
and V
DD1
.............................................................................................................................. 40
2.2.15 V
SS0
and V
SS1
............................................................................................................................... 40
2.2.16 V
PP
(flash memory versions only) ................................................................................................ 40
2.2.17 IC (mask ROM version only) ....................................................................................................... 40
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ....................................... 41
CHAPTER 3 CPU ARCHITECTURE ................................................................................................. 43
3.1 Memory Spaces ....................................................................................................................... 43
3.1.1 Internal program memory space ................................................................................................... 48
3.1.2 Internal data memory space .......................................................................................................... 49
3.1.3 Special function register (SFR) area ............................................................................................. 49
3.1.4 External memory space ................................................................................................................ 49
3.1.5 Data memory addressing .............................................................................................................. 50
3.2 Processor Registers ................................................................................................................ 55
3.2.1 Control registers ............................................................................................................................ 55
3.2.2 General-purpose registers ............................................................................................................ 58
3.2.3 Special function register (SFR) ..................................................................................................... 59