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CHAPTER 13 SERIAL INTERFACE (UART0)
Preliminary User’s Manual U16035EJ1V0UM
(d) Reception
The receive operation is enabled when bit 6 (RXE0) of the asynchronous serial interface mode register 0
(ASIM0) is set (1), and input via the RxD0 pin is sampled.
The serial clock specified by ASIM0 is used to sample the RxD0 pin.
When the RxD0 pin goes low, the 5-bit counter of the baud rate generator begins counting and the start timing
signal for data sampling is output when half of the specified baud rate time has elapsed. If sampling the
RxD0 pin input with this start timing signal yields a low-level result, a start bit is recognized, after which the
5-bit counter is initialized and starts counting and data sampling begins. After the start bit is recognized,
the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame
is completed.
Once reception of one data frame is completed, the receive data in the shift register is transferred to the
receive buffer register 0 (RXB0) and a receive completion interrupt request (INTSR0) occurs.
Even if an error has occurred, the receive data in which the error occurred is still transferred to RXB0. When
ASIM0 bit 1 (ISRM0) is cleared (0) upon occurrence of an error, INTSR0 occurs (see
Figure 13-10
).
When ISRM0 bit is set (1), INTSR0 does not occur.
If the RXE0 bit is reset (0) during a receive operation, the receive operation is stopped immediately. At this
time, the contents of RXB0 and ASIS0 do not change, nor does INTSR0 or INTSER0 occur.
Figure 13-9 shows the timing of the asynchronous serial interface receive completion interrupt request.
Figure 13-9. Timing of Asynchronous Serial Interface Receive Completion Interrupt Request
RxD0 (input)
D0
D1
D2
D6
D7
Parity
STOP
START
INTSR0
Caution
Be sure to read the contents of the receive buffer register 0 (RXB0) even when a receive
error has occurred. Overrun errors will occur during the next data receive operations and
the receive error status will remain until the contents of RXB0 are read.
