FX2N-16CCL-M CC-Link System Master Block
Programming 9
9-15
The timing at which the data in the link special registers (SW) is updated varies depending
on the register number as shown in the table below.
Number
Buffer
memory
Name
Description
SW00B8
6B8
H
Line test 2 result
Stores the line test 2 result.
0 : Normal
Other than 0 : Error code (Refer to Section 13.3.)
SW00B9
6B9
H
EEPROM
registration status
Stores the status of parameter registration to the
EEPROM.
0 : Normal
Other than 0 : Error code (Refer to Section 13.3.)
Table 9.3:
Link special
register
Data update timing
Link special
register
Data update timing
SW0041
Updated independently without
regard to SB
SW0071
Updated independently without
regard to SB
(updated after each station is
stabilized)
SW0045
SW0072
SW0060
Updated when SB0060 changes
SW0074
Updated when SB0074 changes
SW0061
Updated when SB0061 changes
SW0078
Updated when SB0075 changes
SW0062
Updated independently without
regard to SB
SW0080
Updated when SB0080 changes
SW0067
SW0088
Updated independently without
regard to SB
SW0069
SW0098
Updated independently without
regard to SB
SW006A
SW009C
SW006D
SW00B4
SW006E
SW00B8
SW006F
SW00B9
SW0070
⎯
⎯
Summary of Contents for FX2N-16CCL-M
Page 4: ...FX2N 16CCL M CC Link System Master Block ii ...
Page 6: ...FX2N 16CCL M CC Link System Master Block iv ...
Page 34: ...FX2N 16CCL M CC Link System Master Block System Configuration 3 3 14 MEMO ...
Page 66: ...FX2N 16CCL M CC Link System Master Block Specification 4 4 32 MEMO ...
Page 144: ...FX2N 16CCL M CC Link System Master Block Programming 9 9 16 MEMO ...
Page 172: ...FX2N 16CCL M CC Link System Master Block Communication in Compound System 12 12 10 MEMO ...
Page 192: ...FX2N 16CCL M CC Link System Master Block Appendix 14 14 4 MEMO ...
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