FX2N-16CCL-M CC-Link System Master Block
Parameter Setting 7
7-6
M40
SET
M3
SET
K1
D100
H0668
K0
FROM
M8002
Module
error
M20
M35
Initial pulse
Module
ready
M3
When data link startup by
buffer memory parameters
is completed abnormally
Refresh command
M2
M2
PLS
M46
SET
M46
RST
M3
RST
M46
RST
M3
RST
When data link startup by
buffer memory parameters
is completed normally
M26
M27
K1
K4M40
HA
K0
TO
M8000
RUN monitor
M55 to M40
→
BFM#A
H
Summary of Contents for FX2N-16CCL-M
Page 4: ...FX2N 16CCL M CC Link System Master Block ii ...
Page 6: ...FX2N 16CCL M CC Link System Master Block iv ...
Page 34: ...FX2N 16CCL M CC Link System Master Block System Configuration 3 3 14 MEMO ...
Page 66: ...FX2N 16CCL M CC Link System Master Block Specification 4 4 32 MEMO ...
Page 144: ...FX2N 16CCL M CC Link System Master Block Programming 9 9 16 MEMO ...
Page 172: ...FX2N 16CCL M CC Link System Master Block Communication in Compound System 12 12 10 MEMO ...
Page 192: ...FX2N 16CCL M CC Link System Master Block Appendix 14 14 4 MEMO ...
Page 193: ......