Intel® Server Board S2600CW Family TPS
Intel® Server Board S2600CW Platform Management
Revision 2.4
69
Thermal fault indication sensors – These are discrete sensors that indicate a specific
thermal fault condition.
5.3.10.2
Processor DTS-Spec Margin Sensor(s)
Intel® Server Systems supporting the Intel® Xeon® processor E5-2600 v3 and v4 product
families incorporate a DTS based thermal spec. This allows a much more accurate control of
the thermal solution and enables lower fan speeds and lower fan power consumption. The
main usage of this sensor is as an input to the BMC’s fan control algorithms. The BMC
implements this as a threshold sensor. There is one DTS sensor for each installed physical
processor package. Thresholds are not set and alert generation is not enabled for these
sensors. DTS 2.0 is implemented on new Intel board generation DTS 2.0 incorporated
platform-visible thermal data interfaces and internal algorithms for calculating the relevant
thermal data. As the major difference between the DTS 1.0 and DTS 2.0 is that allows the
CPUs to automatically calculate thermal gap/margin to DTS profile as input for Fan Speed
Control. DTS 2.0 helps to further optimize system acoustics. Please refer to iBL #455822
Platform Digital Thermal Sensor (DTS) Based Thermal Specifications and Overview – Rev 1.5
for more details about DTS 2.0
5.3.10.3
Processor Thermal Margin Sensor(s)
Each processor supports a physical thermal margin sensor per core that is readable through
the PECI interface. This provides a relative value representing a thermal margin from the
core’s throttling thermal trip point. Assuming that temp controlled throttling is enabled; the
physical core temp sensor reads ‘0’, which indicates the processor core is being throttled.
The BMC supports one IPMI processor (margin) temperature sensor per physical processor
package. This sensor aggregates the readings of the individual core temperatures in a package
to provide the hottest core temperature reading. When the sensor reads ‘0’, it indicates that
the hottest processor core is throttling.
Due to the fact that the readings are capped at the core’s thermal throttling trip point (reading
= 0), thresholds are not set and alert generation is not enabled for these sensors.
5.3.10.4
Processor Thermal Control Monitoring (Prochot)
The BMC FW monitors the percentage of time that a processor has been operationally
constrained over a given time window (nominally six seconds) due to internal thermal
management algorithms engaging to reduce the temperature of the device. When any
processor core temperature reaches its maximum operating temperature, the processor
package PROCHOT# (processor hot) signal is asserted and these management algorithms,
known as the Thermal Control Circuit (TCC), engage to reduce the temperature, provided TCC
is enabled. TCC is enabled by the BIOS during system boot. This monitoring is instantiated as
one IPMI analog/threshold sensor per processor package. The BMC implements this as a
threshold sensor on a per-processor basis.
Under normal operation, this sensor is expected to read ‘0’ indicating that no processor
throttling has occurred.
