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Intel S2600CW, Technical Product Specification

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Appendix E: POST Code Diagnostic LED Decoder 

Intel® Server Board S2600CW Family TPS 

 

 

Revision 2.4 

182 

Table 94. MRC Progress Codes 

Progress 

Code 

Main Sequence 

Subsequences / 

subfunctions 

0xB0 

Detect DIMM population 

--n/a-- 

0x B1 

Set DDR4 frequency 

--n/a-- 

0x B2 

Gather remaining SPD data 

--n/a-- 

0x B3 

Program registers on the memory controller level  --n/a-- 

0x B4 

Evaluate RAS modes and save rank information 

--n/a-- 

0x B5 

Program registers on the channel level 

--n/a-- 

0x B6 

Perform the JEDEC defined initialization sequence  --n/a-- 

0x B7 

Train DDR4 ranks 

--n/a-- 

0x01 

↓

 

Read DQ/DQS training 

0x02 

↓

 

Receive Enable training 

0x03 

↓

 

Write leveling training 

0x04 

↓

 

Write DQ/DQS training 

0x05 

↓

 

DDR Channel training done 

0x B8 

Initialize CLTT/OLTT 

--n/a-- 

0x B9 

Hardware memory test and init 

--n/a-- 

0x BA 

Execute software memory init 

--n/a-- 

0x BB 

Program memory map and interleaving 

--n/a-- 

0x BC 

Program RAS configuration 

--n/a-- 

0x BF 

MRC is done 

--n/a-- 

 

Memory Initialization at the beginning of POST includes multiple functions, including: 

discovery, channel training, validation that the DIMM population is acceptable and functional, 

Summary of Contents for S2600CW

Page 1: ...Intel Server Board S2600CW Family Technical Product Specification Revision 2 4 March 2017 Intel Server Boards and Systems ...

Page 2: ...ted chapter 5 3 Sensor Monitoring August 2015 1 2 Updated Post Progress Codes and MRC Progress Codes September 2015 1 3 Updated Memory support Table3 4 January 2016 2 0 Updated to Refresh SKU February 2016 2 1 Support for Intel Xeon E5 2600 v4 included May 2016 2 2 Updated Index and Appendix A with DIMM installation information October 2016 2 3 Updated Tables 3 and 4 regarding DIMM support on the ...

Page 3: ...L INJURY OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marke...

Page 4: ...ntel VT for Intel 64 and IA 32 Intel Architecture Intel VT x 21 3 2 2 Intel Virtualization Technology for Directed I O Intel VT d 21 3 2 3 Intel Trusted Execution Technology for Servers Intel TXT 22 3 2 4 Execute Disable 22 3 2 5 Advanced Encryption Standard AES 22 3 2 6 Intel Hyper Threading Technology 22 3 2 7 Intel Turbo Boost Technology 22 3 2 8 Enhanced Intel SpeedStep Technology 23 3 2 9 Int...

Page 5: ...ecurity 54 4 1 BIOS Setup Utility Security Option Configuration 54 4 2 BIOS Password Protection 55 4 3 Trusted Platform Module TPM Support 57 4 3 1 TPM Security BIOS 57 4 3 2 Physical Presence 58 4 3 3 TPM Security Setup Options 58 4 4 Intel Trusted Execution Technology 58 5 Intel Server Board S2600CW Platform Management 60 5 1 Management Feature Set Overview 60 5 1 1 IPMI 2 0 Features Overview 60...

Page 6: ...rrupt Sensor 85 5 3 19 LAN Leash Event Monitoring 85 5 3 20 Add in Module Presence Sensor 86 5 3 21 CMOS Battery Monitoring 86 5 4 Embedded Web Server 86 5 5 Advanced Management Feature Support RMM4 Lite 88 5 5 1 Keyboard Video Mouse KVM Redirection 90 5 5 2 Remote Console 91 5 5 3 Performance 91 5 5 4 Security 92 5 5 5 Availability 92 5 5 6 Usage 92 5 5 7 Force enter BIOS Setup 92 5 5 8 Media Red...

Page 7: ...Connectors 103 7 4 1 RMM4 Lite Connector 103 7 4 2 TPM Connector 104 7 4 3 PMBus Connector 104 7 4 4 Chassis Intrusion Header 104 7 4 5 IPMB Connector 105 7 5 FAN Connectors 105 7 5 1 System FAN Connectors 105 7 5 2 CPU FAN Connector 105 7 6 Serial Port and Video Connectors 106 7 6 1 Serial Port Connector 106 7 6 2 Video Connector 106 7 7 PCIe Riser Slot 107 8 Intel Server Board S2600CW Jumper Blo...

Page 8: ...7 Thermal CLST 135 10 2 8 Power Supply Diagnostic Black Box 135 10 2 9 Firmware Uploader 135 10 3 Higer Power Common Redundant Power Distribution Board PDB 136 10 3 1 Mechanical Overview 136 10 3 2 DC Output Specification 137 10 3 3 Protection Circuits 147 10 3 4 PWOK Power OK Signal 148 10 3 5 PSON Signal 148 10 3 6 PMBus 148 11 Design and Environmental Specifications 149 11 1 Intel Server Board ...

Page 9: ...Intel Server Board S2600CW Family TPS Table of Contents Revision 2 4 ix ...

Page 10: ...Socket Assembly 17 Figure 14 Memory Subsystem for Intel Server Board S2600CW 24 Figure 15 Intel Server Board S2600CW DIMM Slot Layout 27 Figure 16 BIOS Setup Utility Video Configuration Options 49 Figure 17 TPM Module 51 Figure 18 High level Fan Speed Control Process 80 Figure 19 Intel RMM4 Lite Activation Key Location 89 Figure 20 Video Connector Pin out 107 Figure 21 Jumper Blocks 111 Figure 22 ...

Page 11: ...Power Connector Pin out 98 Table 16 CPU_2 Power Connector Pin out 98 Table 17 Front Panel Header Pin out 99 Table 18 Front Panel USB 3 0 Connector Pin out 100 Table 19 SATA 6Gbps Connector Pin out 100 Table 20 Mini SAS HD Connectors for SATA 6Gbps Pin out 100 Table 21 Mini SAS HD Connectors for SAS 12Gbps Pin out 101 Table 22 HSBP I2 C Header Pin out 101 Table 23 HDD LED Header Pin out 102 Table 2...

Page 12: ...Regulation Limits 128 Table 52 Transient Load Requirements 128 Table 53 Capacitive Loading Conditions 128 Table 54 Ripples and Noise 130 Table 55 Timing Requirements 130 Table 56 Over Current Protection 132 Table 57 Over Voltage Protection OVP Limits 132 Table 58 PSON Signal Characteristic 133 Table 59 PWOK Signal Characteristics 134 Table 60 SMBAlert Signal Characteristics 134 Table 61 Thermal Re...

Page 13: ...e and Noise 145 Table 83 Output Voltage Timing 146 Table 84 PDB Over Current Protection Limits 240VA Protection 147 Table 85 Over Voltage Protection OVP Limits 147 Table 86 System PWOK Requirements 148 Table 87 PDB Addressing 148 Table 88 Server Board Design Specifications 149 Table 89 MTBF Estimate 150 Table 90 Compatible Intel Server Chassis 152 Table 91 Integrated BMC Core Sensors 155 Table 92 ...

Page 14: ...List of Tables Intel Server Board S2600CW Family TPS Revision 2 4 xiv This page intentionally left blank ...

Page 15: ...on Chapter 2 Intel Server Board S2600CW Overview Chapter 3 Intel Server Board S2600CW Functional Architecture Chapter 4 System Security Chapter 5 Intel Server Board S2600CW Platform Management Chapter 6 Intel Intelligent Power Node Manager NM Support Overview Chapter 7 Intel Server Board S2600CW Connector Header Locations and Pin outs Chapter 8 Intel Server Board S2600CW Jumper Blocks Chapter 9 In...

Page 16: ...are used together the fully integrated system meets the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot...

Page 17: ...W Feature Set Feature Description Processors Two LGA2011 3 Socket R3 processor sockets Support for one or two Intel Xeon E5 2600 v3 or V4 processors product family Maximum supported Thermal Design Power TDP of up to 145 W Memory Eight memory channels four channels for each processor socket Two DIMM slots for each channel Registered DDR4 RDIMM Load Reduced DDR4 LRDIMM DDR4 Memory data transfer rate...

Page 18: ...i SAS HD connectors supporting eight SAS 12Gbps transfer rate S2600CW2SR and S2600CWTSR only One 2x10 pin connector providing front panel support for two USB 3 0 ports One internal Type A USB 2 0 port One internal USB port to support low profile eUSB SSD One DH 10 Serial Port B connector One 24 pin SSI EEB compliant front panel header One TPM connector One M 2 NGFF connector One RMM4 LITE connecto...

Page 19: ...TPS Intel Server Board S2600CW Overview Revision 2 4 5 2 2 Server Board Layout The following diagram shows the board layout for S2600CW2SR and S2600CWTSR with on board SAS controller Figure 1 Intel Server Board S2600CW2SR and S2600CWTSR ...

Page 20: ...00CW Overview Intel Server Board S2600CW Family TPS 6 Revision 2 4 The following diagram shows the board layout for S2600CW2R and S2600CWTR without on board SAS controller Figure 2 Intel Server Board S2600CW2R and S2600CWTR ...

Page 21: ...sion 2 4 7 2 2 1 Server Board Connector and Component Layout The following figure shows the layout of the server board and the location of each connector and major component except jumpers The locations of jumpers can be found in Chapter 8 Figure 3 Connector and Component Layout ...

Page 22: ...Intel Server Board S2600CW Overview Intel Server Board S2600CW Family TPS 8 Revision 2 4 2 2 2 Server Board Mechanical Drawings Figure 4 Mounting Hole Locations 1 of 2 ...

Page 23: ...Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Overview Revision 2 4 9 Figure 5 Mounting Hole Locations 2 of 2 ...

Page 24: ...Intel Server Board S2600CW Overview Intel Server Board S2600CW Family TPS 10 Revision 2 4 Figure 6 Major Connector Pin 1 Locations 1 of 2 ...

Page 25: ...Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Overview Revision 2 4 11 Figure 7 Major Connector Pin 1 Locations 2 of 2 ...

Page 26: ...Intel Server Board S2600CW Overview Intel Server Board S2600CW Family TPS 12 Revision 2 4 Figure 8 Primary Side Card Side Keep out Zone ...

Page 27: ...Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Overview Revision 2 4 13 Figure 9 Second Side Keep out Zone ...

Page 28: ... I O Layout The following drawing shows the layout of the rear I O components for the server boards Callout Description Callout Description A Video B USB 2 0 C Dedicated Management NIC DMN D USB 3 0 E NIC1 F NIC2 G Diagnostic LEDs H ID LED I System Status LED Figure 10 Rear I O Layout of Intel Server Board S2600CW ...

Page 29: ...ure and design of the Intel Server Board S2600CW is based on the Intel Xeon E5 2600 v3 and v4 processors and the Intel C612 chipset This chapter provides a high level description of the functionality associated with each chipset component and the architectural blocks that make up the server boards Figure 11 Intel Server Board S2600CW2R S2600CWTR Functional Block Diagram ...

Page 30: ...v4 product families with a Thermal Design Power TDP of up to 145W Previous generation Intel Xeon processors are not supported on the Intel Server Boards described in this document Visit the Intel website for a complete list of supported processors 3 1 1 Processor Socket Assembly Each processor socket of the server board is pre assembled with an Independent Latching Mechanism ILM and Back Plate whi...

Page 31: ...rocessor socket labeled CPU1 When two processors are installed the following population rules apply Both processors must be of the same processor family Both processors must have the same number of cores Both processors must have the same cache sizes for all levels of processor cache memory Processors with different core frequencies can be mixed in a system given the prior rules are met If this co...

Page 32: ...system For Fatal Errors during processor initialization the System Status LED will be set to a steady Amber color indicating an unrecoverable system failure condition Major If the Post Error Pause setup option is enabled the system goes directly to the Error Manager to display the error and logs the POST Error Code to the SEL Operator intervention is required to continue booting the system Otherwi...

Page 33: ... Processor cache not identical Fatal The BIOS detects the error condition and responds as follows Logs the POST Error Code into the SEL Alerts the BMC to set the System Status LED to steady Amber Displays 0192 Processor cache size mismatch detected message in the Error Manager Takes Fatal Error action see above and will not boot until the fault condition is remedied Processor frequency speed not i...

Page 34: ...Setup Processor microcode update failed Major The BIOS detects the error condition and responds as follows Logs the POST Error Code into the SEL Displays 816x Processor 0x unable to apply microcode update message in the Error Manager or on the screen Takes Major Error action The system may continue to boot in a degraded state depending on the setting of POST Error Pause in Setup or may halt with t...

Page 35: ...vanced Encryption Standard AES Intel Hyper Threading Technology Intel Turbo Boost Technology Enhanced Intel SpeedStep Technology Intel Advanced Vector Extensions 2 Intel AVX2 Intel Node Manager 3 0 Intel Secure Key Intel OS Guard Intel Quick Data Technology Trusted Platform Module TPM 1 2 3 2 1 Intel Virtualization Technology Intel VT for Intel 64 and IA 32 Intel Architecture Intel VT x Intel VT p...

Page 36: ...determines the identity of the controlling environment by accurately measuring and verifying the controlling software 3 2 4 Execute Disable Intel s Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system This allows the processor to classify areas in memory by where application code can execute and whe...

Page 37: ...ickly under Enhanced Intel SpeedStep Technology 3 2 9 Intel Advanced Vector Extensions 2 Intel AVX2 Intel Advanced Vector Extensions 2 0 Intel AVX2 is the latest expansion of the Intel instruction set Intel AVX2 extends the Intel Advanced Vector Extensions Intel AVX with 256 bit integer instructions floating point fused multiply add FMA instructions and gather operations The 256 bit integer vector...

Page 38: ...AND Instruction usage including code examples 3 2 12 Intel OS Guard Intel OS Guard protects the operating system OS from applications that have been tampered with or hacked by preventing an attack from being executed from application memory Intel OS Guard also protects the OS from malware by blocking application access to critical OS vectors 3 2 13 Trusted Platform Module TPM Trusted Platform Modu...

Page 39: ...mmand and address DDR4 Command Address parity check and retry Intra socket memory mirroring Memory demand and patrol scrubbing HA and IMC corrupt data containment Rank level memory sparing Multi rank level memory sparing Failed DIMM isolation 3 3 1 Supported Memory Table 3 DDR4 RDIMM LRDIMM Support with Intel Xeon E5 2600 V3 Type Ranks Per DIMM and Data Width Memory Capacity Per DIMM Speed MT s an...

Page 40: ...emory channels from processor socket 2 are identified as Channel E F G and H Each memory slot on the server board is identified by channel and slot number within that channel For example DIMM_A1 is the first slot on Channel A on processor 1 DIMM_E1 is the first DIMM socket on Channel E on processor 2 The memory slots associated with a given processor are unavailable if the corresponding processor ...

Page 41: ...he nomenclature for DIMM sockets on the Intel Server Board S2600CW is detailed in the following table Table 5 Intel Server Board S2600CW DIMM Nomenclature Processor Socket 1 Processor Socket 2 0 Channel A 1 Channel B 2 Channel C 3 Channel D 0 Channel A 1 Channel B 2 Channel C 3 Channel D A1 A2 B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 G1 G2 H1 H2 Figure 15 Intel Server Board S2600CW DIMM Slot Layout The follo...

Page 42: ...t Channel Mode the amount of installed physical memory is the amount of effective memory available There is no reduction Independent Channel mode is also known as Maximum Performance mode Lockstep Mode For Lockstep Mode the amount of installed physical memory is the amount of effective memory available There is no reduction Lockstep Mode only changes the addressing to address two channels in paral...

Page 43: ...bullet above If Quiet Boot is disabled the BIOS displays the total system memory on the diagnostic screen at the end of POST This total is the same as the amount described by the first bullet above The BIOS provides the total amount of memory in the system by supporting the EFI Boot Service function GetMemoryMap The BIOS provides the total amount of memory in the system by supporting the INT 15h E...

Page 44: ...ory Demand and Patrol Scrubbing Demand scrubbing is the ability to write corrected data back to the memory once a correctable error is detected on a read transaction Patrol scrubbing proactively searches the system memory repairing correctable errors It prevents accumulation of single bit errors HA and IMC Corrupt Data Containment Corrupt Data Containment is a process of signaling memory patrol sc...

Page 45: ...here are no other detectable DIMMs in the system The undetected DIMM could result later in an invalid configuration if the no SPD DIMM is in Slot 1 or 2 ahead of other DIMMs on the same channel DIMM SPD read error This DIMM will be disabled POST Error Codes 856x SPD Error and 854x DIMM Disabled will be generated If all DIMMs are failed this will result in a Fatal Error Halt 0xE8 All DIMMs on the c...

Page 46: ... be a DR or SR DIMM Mixed DIMM Types A mixture of RDIMMs and or LRDIMMs is not allowed A mixture of LRDIMMs operating in Direct Map mode and Rank Multiplication mode is also not allowed This will result in a POST Error Code 8501 DIMM Population Error and Population Error Fatal Error Halt 0xED Mixed DIMM Parameters Within an RDIMM or LRDIMM configuration mixtures of valid DIMM technologies sizes sp...

Page 47: ...r Code 854x DIMM Disabled This results in a momentary Error Display 0xEB and if all DIMMs have failed this will result in a Fatal Error Halt 0xE8 No usable memory installed If no enabled and available memory remains this will result in a Fatal Error Halt 0xE8 The ECC functionality is enabled after all of memory has been cleared to zeroes to make sure that the data bits and the ECC bits are in agre...

Page 48: ...Ie Gen III x16 electrical with x16 physical connector From the second processor Slot 2 PCIe Gen III x16 electrical with x16 physical connector Slot 3 PCIe Gen III x8 electrical with x8 physical connector Slot 4 PCIe Gen III x16 electrical with x16 physical connector The server board supports up to three full length full height double width PCIe cards on slot 2 slot 4 and slot 6 Standard PCIe slots...

Page 49: ...BIOS encounters a PCI PCI bridge device Scanning continues on the secondary side of the bridge until all subordinate buses are assigned numbers PCI bus number assignments may vary from boot to boot with varying presence of PCI devices with PCI PCI bridges If a bridge device with a single bus behind it is inserted into a PCI bus all subsequent PCI bus numbers below the current bus are increased by ...

Page 50: ...B 0x80 2 1 PCIE Slot2 PCIE Slot2 PE2C 0x80 2 2 PCIE Slot2 PCIE Slot2 PE2D 0x80 2 3 PCIE Slot2 PCIE Slot2 PE3A 0x80 3 0 PCIE Slot4 PCIE Slot4 PE3B 0x80 3 1 PCIE Slot4 PCIE Slot4 PE3C 0x80 3 2 PCIE Slot4 PCIE Slot4 PE3D 0x80 3 3 PCIE Slot4 PCIE Slot4 DMI N A N A N A Not connected Not connected 3 4 3 PCIe Non Transparent Bridge NTB PCI Express Non Transparent Bridge NTB acts as a gateway that enables...

Page 51: ... Intel Xeon Processor E5 2600 Product Families system Note When NTB is enabled Spread Spectrum Clocking SSC is required to be disabled at each NTB link 3 4 4 PCIe SSD Support The board supports PCIe SSD as cabled add in card on existing PCIe slots The x16 PCIe add in card can support up to four x4 PCIe SSD 2 5 drives with mini SAS HD cables connected to the hot swap backplane The ingredients for P...

Page 52: ... Support The Intel C612 Series chipset provides the server board with support for up to ten Serial ATA SATA ports from two integrated controllers identified as SATA and sSATA The Intel Server Board S2600CW family on board SATA connectors include Two 7 pin single port SATA connectors labeled SATA 4 and SATA 5 each port is capable of supporting up to 6 Gbps These connectors are intended for use with...

Page 53: ...M 2 formerly known as the Next Generation Form Factor NGFF is a specification for computer expansion cards and associated connectors It is a small form factor module supporting SSD Memory offloading technology using SATA or PCIe x4 links The server board uses a SATA mux to select between M 2 NGFF connector and 7 pin SATA connector Note Although M 2 NGFF allows support for many different interfaces...

Page 54: ... the board The following diagram shows how the M 2 NGFF modules are installed on the connector Note The insertion angle may vary 3 4 8 Embedded SATA RAID Support The Intel Server Board S2600CW2R S2600CWTR has embedded support for two SATA SW RAID options Intel Rapid Storage Technology RSTe 4 0 Intel Embedded Server RAID Technology 2 ESRT2 based on LSI MegaRAID SW RAID technology ...

Page 55: ...0 requires 4 hard drives and provides the capacity of two drives RAID Level 5 provides highly efficient storage while maintaining fault tolerance on 3 or more drives By striping parity and rotating it across all disks fault tolerance of any single drive is achieved while only consuming 1 drive worth of capacity That is a 3 drive RAID 5 has the capacity of 2 drives or a 4 drive RAID 5 has the capac...

Page 56: ...he user with a status of the RAID volumes at each boot up 3 4 8 2 Intel Embedded Server RAID Technology 2 ESRT2 Features of ESRT2 include the following Based on LSI MegaRAID Software Stack Software RAID with system providing memory and CPU utilization Native support for RAID Levels 0 1 10 Optional support for RAID Level 5 Enabled with the addition of an optionally installed SATA RAID 5 Upgrade Key...

Page 57: ...2600CW2SR S2600CWTSR supports a Gen3 12G SAS IO Controller with LSISAS3008 S2600CW2R S2600CWTR does not support this The 8 port SAS 12G or SATA 6G will connect to a 1x2 Right Angle RA mini SAS HD connector and be used for Hot Swap Backplane HSBP connectivity The following list summarizes the features of the LSISAS3008 controller Providing an eight lane 8Gbps PCIe 3 0 host interface Providing an ei...

Page 58: ... 10 Integrated MegaRAID Support Integrated MegaRaid RAID IMR RAID 0 1 10 support is included with based LSISAS3008 functionality Integrated MegaRaid IMR RAID 5 upgrade is supported through installation of an activation key The following diagram identifies the location of the activation key for the IMR RAID 5 ...

Page 59: ...on the board providing USB connectivity to the front panel One Type A USB header on the board 3 4 11 2 eUSB Module Smart Modular Z U130 Value Solid State Drive SSD is an embedded USB2 0 eUSB2 0 storage solution built around high performance Intel NAND flash memory This module uses single level cell Intel NAND flash memory with cache programming and dual plane feature set designed to improve overal...

Page 60: ...ection of the server board Utilizing the optional front panel video connector may result in lower video resolutions 3 4 12 1 Dual Video and Add In Video Adapters There are enable disable options in the F2 BIOS Setup PCI Configuration screen for Add in Video Adapter and Onboard Video When Onboard Video is Enabled and Add in Video Adapter is also Enabled then both video displays can be active The on...

Page 61: ...o mode the onboard video controller or the add in video adapter is detected during the POST In the dual video mode the onboard video controller is enabled and is the primary video device while the add in video adapter is allocated resources and is considered as the secondary video device 3 4 12 1 2 Configuration Cases Multi CPU Socket Boards and Add In Video Adapters Because this combination of CP...

Page 62: ...led grayout can t change When there are add in video cards connected to both CPU Socket 1 2 Case 7 Onboard video active display add in video on Socket 1 and Add in video on Socket 2 don t actively display Onboard Video Enabled Legacy VGA Socket CPU Socket 1 Add in Video Adapter Disabled Case 8 Add in video on Socket 1 active display onboard video and Add in video on Socket 2 don t actively display...

Page 63: ... Help Text If enabled the Add in video adapter works as primary video device during POST if installed If disabled the on board video controller becomes the primary video device Comments This option must be enabled to use an add in card as a primary POST Legacy Video device If there is no add in video card in any PCIe slot connected to CPU Socket 1 with the Legacy VGA Socket option set to CPU Socke...

Page 64: ...ble with a value set to Disabled This is because the Onboard Video is connected to CPU Socket 1 and is not functional when CPU Socket 2 is the active path for video When Legacy VGA Socket is set back to CPU Socket 1 this option becomes available again and is set to its default value of Enabled Note This option does not appear on some models 3 Legacy VGA Socket Option Values CPU Socket 1 CPU Socket...

Page 65: ...e TPM provides platform security functions such as hash encryption and secure storage and works in conjunction with the processor s TXT functionality The TPM is a small board that provides hardware level security for the server and resides on the LPC bus Figure 17 TPM Module 3 4 14 Network Support The Intel Server Board S2600CW2R S2600CW2SR provides 1Gb network connectivity with the Intel I350 dua...

Page 66: ...he NIC 1 MAC address 2 Integrated BMC LAN Channel MAC1 address Assigned the NIC 1 MAC address 3 Intel Remote Management Module Intel RMM MAC address Assigned the NIC 1 MAC address 4 The server board S2600CWTR S2600CWTSR X540 has the following MAC addresses assigned NIC 1 MAC address NIC 2 MAC address Assigned the NIC 1 MAC address 1 Integrated BMC LAN Channel MAC0 address Assigned the NIC 1 MAC ad...

Page 67: ...D and indicates network connection when on and transmit receive activity when blinking The LED at the right of the connector indicates link speed as defined in the following table Table 7 External RJ45 NIC Port LED Definition LED Color LED State NIC State Green Amber Right Off 3rd Fastest 100 Mbps for X540 Amber Yellow 2nd Fastest 1 Gbps for X540 Green Fastest 10 Gbps for X540 Green Left On Active...

Page 68: ...curity Option Configuration The F2 BIOS Setup Utility accessed during POST includes a Security tab where options to configure passwords front panel lockout and TPM settings can be found Main Advanced Security Server Management Boot Options Boot Manager Administrator Password Status Installed Not Installed User Password Status Installed Not Installed Set Administrator Password 123aBcDeFgH Set User ...

Page 69: ...and activates TPM Turn Off Disables and deactivates TPM Clear Ownership Removes the TPM ownership authentication and returns the TPM to a factory default state Note The BIOS setting returns to No Operation on every boot cycle by default 4 2 BIOS Password Protection The BIOS uses passwords to prevent unauthorized tampering with the server setup Passwords can restrict entry to the BIOS Setup restric...

Page 70: ... enter the BIOS setup The Administrator has control over all fields in the BIOS setup including the ability to clear the User password and the Administrator password It is strongly recommended that at least an Administrator Password be set because not having set a password gives everyone who boots the system the equivalent of Administrative access Unless an Administrator password is installed any ...

Page 71: ...s it hands off control to the operating system loader and in turn to the operating system If the operating system is TPM enabled it compares the BIOS TPM measurements to those of previous boots to make sure the system was not tampered with before continuing the operating system boot process Once the operating system is in operation it optionally uses TPM to provide additional system and data secur...

Page 72: ...ents After the requested TPM BIOS Setup operation is carried out the option reverts to No Operation The BIOS TPM Setup also displays the current state of the TPM whether TPM is enabled or disabled and activated or deactivated Note that while using TPM a TPM enabled operating system or application may change the TPM state independently of the BIOS setup When an operating system modifies the TPM sta...

Page 73: ...e Modules and an Intel Trusted Execution Technology compatible measured launched environment MLE The MLE could consist of a virtual machine monitor an OS or an application In addition Intel Trusted Execution Technology requires the system to include a TPM v1 2 as defined by the Trusted Computing Group TPM PC Client Specifications Revision 1 2 When available Intel Trusted Execution Technology can b...

Page 74: ... Server System BIOS External Product Specification EPS for Intel Server Products based on the Intel Xeon processor E5 2600 v3 and v4 product families should be referenced for more in depth and design level platform management information 5 1 Management Feature Set Overview The following sections outline features that the integrated BMC firmware can support Support and utilization for some features...

Page 75: ...nt Interface Specification Second Generation v2 0 5 1 2 Non IPMI Features Overview The BMC supports the following non IPMI features In circuit BMC firmware update Fault resilient booting FRB FRB2 is supported by the watchdog timer functionality Chassis intrusion detection dependent on platform support Fan speed control with SDR Fan redundancy monitoring and support Enhancements to fan speed contro...

Page 76: ...bedded web server Human readable SEL Additional system configurability Additional system monitoring capability Enhanced online help Integrated KVM Enhancements to KVM redirection Support for higher resolution Integrated Remote Media Redirection Lightweight Directory Access Protocol LDAP support Intel Intelligent Power Node Manager support Embedded platform debug feature which allows capture of det...

Page 77: ...Capabilities Power button Front panel power button Turns power on or off BMC watchdog timer Internal BMC timer Turns power off or power cycle BMC chassis control Commands Routed through command processor Turns power on or off or power cycle Power state retention Implemented by means of BMC internal logic Turns power on when AC power returns Chipset Sleep S4 S5 signal same as POWER_ON Turns power o...

Page 78: ...orithms and hardware support that allow a multiprocessor system to boot even if the bootstrap processor BSP fails Only FRB2 is supported using watchdog timer commands FRB2 refers to the FRB algorithm that detects system failures during POST The BIOS uses the BMC watchdog timer to back up its operation during POST The BIOS configures the watchdog timer to indicate that the BIOS is using the timer f...

Page 79: ...e SEL timestamps may not be in order Up to 3 639 SEL records can be stored at a time Because the SEL is circular any command that results in an overflow of the SEL beyond the allocated space will overwrite the oldest entries in the SEL while setting the overflow flag 5 3 Sensor Monitoring The BMC monitors system hardware and reports system health The information gathered from physical sensors is t...

Page 80: ...esignated as auto rearm IPMI command Re arm Sensor Event BMC internal method The BMC may re arm certain sensors due to a trigger condition For example some sensors may be re armed due to a system reset A BMC reset will re arm all sensors System reset or DC power cycle will re arm all system fan sensors 5 3 2 2 Re arm and Event Generation All BMC owned sensors that show an asserted event status gen...

Page 81: ...to log SEL events due to expirations of the IPMI 2 0 compliant Watchdog Timer 5 3 6 BMC Watchdog Sensor The BMC supports an IPMI sensor to report that a BMC reset has occurred due to an action taken by the BMC Watchdog feature A SEL event will be logged whenever either the BMC FW stack is reset or the BMC CPU itself is reset 5 3 7 BMC System Management Health Monitoring The BMC tracks the health o...

Page 82: ... analog threshold sensors with the exception of Processor Temperature sensors critical and non critical thresholds upper and lower are set through SDRs and event generation enabled for both assertion and de assertion events For discrete sensors both assertion and de assertion event generation are enabled Mandatory monitoring of platform thermal sensors includes Inlet temperature physical sensor is...

Page 83: ...readable through the PECI interface This provides a relative value representing a thermal margin from the core s throttling thermal trip point Assuming that temp controlled throttling is enabled the physical core temp sensor reads 0 which indicates the processor core is being throttled The BMC supports one IPMI processor margin temperature sensor per physical processor package This sensor aggregat...

Page 84: ...e of baseboard can be used as inlet temperature sensor with several degrees offset from actual inlet temperature 5 3 10 7 Baseboard Ambient Temperature Sensor s The server baseboard provides one or more physical thermal sensors to monitor the ambient temperature of a board location This is typically to provide rudimentary thermal monitoring of components that lack internal thermal sensors 5 3 10 8...

Page 85: ...ects that a module is installed it will attempt to access the physical thermal sensor and if found enable the associated IPMI temperature sensor 5 3 10 13 Processor ThermTrip When a Processor ThermTrip occurs the system hardware will automatically power down the server If the BMC detects that a ThermTrip occurs it will set the ThermTrip offset for the applicable processor status sensor 5 3 10 14 S...

Page 86: ...fset has been asserted it remains asserted until one of the following happens 1 A Rearm Sensor Events command is executed for the processor status sensor 2 An AC or DC power cycle system reset or system boot occurs The BMC provides system status indication to the front panel LEDs for processor fault conditions shown in Table 11 CPU Presence status is not saved across AC power cycles and therefore ...

Page 87: ...ot be communicated to the core to trigger SMI ERR 2 events are fatal error conditions where the BIOS and OS will attempt to gracefully handle error but may not be always do so reliably A continuously asserted ERR2 signal is an indication that the BIOS cannot service the condition that caused the error This is usually because that condition prevents the BIOS from running When an ERR2 timeout occurs...

Page 88: ...PU slot into an event data byte in the SEL entry If PECI is non functional it isn t guaranteed in this situation then the OEM code should indicate that the source is unknown Event data byte 2 and byte 3 for CATERR sensor SEL events ED1 0xA1 ED2 CATERR type 0 Unknown 1 CATERR 2 CPU Core Error not supported on Intel Server Systems supporting the Intel Xeon processor E5 2600 v3 and v4 product familie...

Page 89: ...d for fan failure detection The reported sensor reading is proportional to the fan s RPM This monitoring capability is instantiated in the form of IPMI analog threshold sensors Most fan implementations provide for a variable speed fan so the variations in fan speed can be large Therefore the threshold values must be set sufficiently low as to not result in inappropriate threshold crossings Fan tac...

Page 90: ...e IPMI sensor if a fan failure is detected Power supply fan sensors are implemented as manual re arm sensors because a failure condition can result in boosting of the fans This in turn may cause a failing fan s speed to rise above the fault threshold and can result in fan oscillations As a result these sensors do not auto rearm when the fault condition goes away but rather are rearmed only when th...

Page 91: ...n have a set of temperature and fan sensors associated with it These are used to determine the current fan domain state A fan domain has three states The sleep and boost states have fixed but configurable through OEM SDRs fan speeds associated with them The nominal state has a variable speed determined by the fan domain policy An OEM SDR record is used to configure the fan domain policy The fan do...

Page 92: ...tes as determined by the number and health of the fans The definition of fan redundancy is configuration dependent The BMC allows redundancy to be configured on a per fan redundancy sensor basis through OEM SDR records A fan failure or removal of hot swap fans up to the number of redundant fans specified in the SDR in a fan configuration is a non critical failure and is reflected in the front pane...

Page 93: ...n speed transitions If a Tcontrol SDR record does not contain a hysteresis definition for example an SDR adhering to a legacy format the BMC assumes a hysteresis value of zero 5 3 14 5 Thermal and Acoustic Management This feature refers to enhanced fan management to keep the system optimally cooled while reducing the amount of noise generated by the system fans Aggressive acoustics standards might...

Page 94: ...cture creating the resulting fan speeds Figure 18 High level Fan Speed Control Process 5 3 14 6 1 Processor Thermal Management Processor thermal management utilizes clamp algorithms for which the Processor DTS Spec margin sensor is a controlling input This replaces the use of the legacy raw DTS sensor reading that was utilized on previous generation platforms The legacy DTS sensor is retained only...

Page 95: ... run as a closed loop system with the DIMM temperature sensors as the control input Adjustments are made to the throttling during runtime based on changes in system cooling fan speed Intel Server Systems supporting the Intel Xeon processor E5 2600 v3 and v4 product families introduce a new type of CLTT which is referred to as Hybrid CTLL for which the integrated Memory controller estimates the DRA...

Page 96: ...ically understand configuration details and automatically select the optimal fan speed control profile in the BMC Customers will only select a performance or an acoustic profile selection from the BIOS menu for EPSD system and the fan speed control will be optimal for the configuration loaded Users can still choose performance or acoustic profile in BIOS setting Default is acoustic Performance opt...

Page 97: ...l other fan domains An OEM SDR table defines the response of each fan domain based on a failure of any fan including both system and power supply fans for PMBus compliant power supplies only This means that if a system has six fans there will be six different fan fail reactions 5 3 14 9 Programmable Fan PWM Offset The system provides a BIOS Setup option to boost the system fan speed by a programma...

Page 98: ...in and out to adjust the power capacity and the BMC will adjust the Redundancy status accordingly The definition of redundancy is power subsystem dependent and sometimes even configuration dependent See the appropriate Platform Specific Information for power unit redundancy support This sensor is configured as manual rearm sensor in order to avoid the possibility of extraneous SEL events that coul...

Page 99: ... 12 Component Fault LEDs Component Owner Color State Description Fan Fault LED BMC Amber Solid On Fan failed Amber Off Fan working correctly DIMM Fault LED BMC Amber Solid On Memory failure detected by the BIOS Amber Off DIMM working correctly HDD Fault LED HSBP PSoC Amber On HDD Fault Amber Blink Predictive failure rebuild identify Amber Off Ok no errors CPU Fault LEDs BMC Amber off Ok no errors ...

Page 100: ...MC Base manageability provides an embedded web server and an OEM customizable web GUI which exposes the manageability features of the BMC base feature set It is supported over all on board NICs that have management connectivity to the BMC as well as an optional dedicated add in management NIC At least two concurrent web sessions from up to two different users is supported The embedded web user int...

Page 101: ...configurable refresh rate Online help Display clear SEL display is in easily understandable human readable format Supports major industry standard browsers Microsoft Internet Explorer and Mozilla Firefox The GUI session automatically times out after a user configurable inactivity period By default this inactivity period is 30 minutes Embedded Platform Debug feature Allow the user to initiate a deb...

Page 102: ...grated baseboard management controller has support for advanced management features which are enabled when an optional Intel Remote Management Module 4 Lite RMM4 Lite is installed The Intel RMM4 add on offers convenient remote KVM access and control through LAN and internet It captures digitizes and compresses video and transmits it with keyboard and mouse signals to and from a remote computer Rem...

Page 103: ... X X Embedded Web Server X X SSH Support X X Integrated KVM X Integrated Remote Media Redirection X Lightweight Directory Access Protocol LDAP X X Intel Intelligent Power Node Manager Support X X SMASH CLP X X On the server board the Intel RMM4 Lite key is installed at the following location Figure 19 Intel RMM4 Lite Activation Key Location The server board includes a dedicated 1GbE RJ45 Managemen...

Page 104: ...media redirection applets The BMC supports an embedded KVM application Remote Console that can be launched from the embedded web server from a remote console USB1 1 or USB 2 0 based mouse and keyboard redirection are supported It is also possible to use the KVM redirection KVM r session concurrently with media redirection media r This feature allows a user to interactively use the keyboard video a...

Page 105: ...or CDROM media redirection and 5123 for Floppy USB media redirection When encryption is enabled the protocol uses ports 7582 for KVM 5124 for CDROM media redirection and 5127 for Floppy USB media redirection The local network environment must permit these connections to be made that is the firewall and in case of a private internal network the NAT Network Address Translation settings have to be co...

Page 106: ...5 5 7 Force enter BIOS Setup KVM redirection can present an option to force enter BIOS Setup This enables the system to enter F2 setup while booting which is often missed by the time the remote console redirects the video 5 5 8 Media Redirection The embedded web server provides a Java applet to enable remote media redirection This may be used in conjunction with the remote KVM feature or as a stan...

Page 107: ...rder and it is possible to change the BIOS boot order to boot from this remote device It is possible to install an operating system on a bare metal server no OS present using the remotely mounted device This may also require the use of KVM r to configure the OS during install USB storage devices will appear as floppy disks over media redirection This allows for the installation of device drivers d...

Page 108: ...Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS 94 Revision 2 4 ...

Page 109: ...limiting PMBus compliant power supplies provide the capability to monitor input power consumption which is necessary to support NM The NM architecture applicable to this generation of servers is defined by the NPTM Architecture Specification v2 0 NPTM is an evolving technology that is expected to continue to add new capabilities that will be defined in subsequent versions of the specification The ...

Page 110: ...he NM feature is supported on that product This OEM SDR is used by management software to detect whether NM is supported and to understand how to communicate with it Since PMBus compliant power supplies are required in order to support NM the system should be probed when the SDRs are loaded into the BMC s SDR repository in order to determine whether the installed power supplies do in fact support ...

Page 111: ...n It is expected that the interruption to the fans will be of short enough duration to avoid false lower threshold crossings for the fan tach sensors however this may need to be comprehended by the fan monitoring FW if it does have this side effect ME FW will log an event into the SEL to indicate when the system has been throttled by the SmaRT CLST power management feature This is dependent on ME ...

Page 112: ...nector Pin out Pin Signal Name Pin Signal Name 1 P3V3 13 P3V3 2 P3V3 14 N12V 3 GND 15 GND 4 P5V 16 FM_PS_EN_PSU_ON 5 GND 17 GND 6 P5V 18 GND 7 GND 19 GND 8 PWRGD_PS_PWROK_PSU_R1 20 NC_PS_RES_TP 9 P5V_STBY_PSU 21 P5V 10 P12V 22 P5V 11 P12V 23 P5V 12 P3V3 24 GND 7 1 2 CPU Power Connectors On the server board are two white 8 pin CPU power connectors labeled CPU_1 PWR and CPU_2 PWR The following table...

Page 113: ... Drive Activity LEDs System Status LED System ID LED The following table provides the pin out for this 24 pin header Table 17 Front Panel Header Pin out Pin Signal Name Pin Signal Name 1 P3V3_AUX 2 P3V3_AUX 3 Key 4 P5V_STBY 5 FP_PWR_LED_BUF_N 6 FP_ID_LED_BUF_N 7 P3V3 8 FP_LED_STATUS_GREEN_BUF_N 9 LED_HDD_ACTIVITY_N 10 FP_LED_STATUS_AMBER_BUF_N 11 FP_PWR_BTN_N 12 LED_NIC_LINK0_ACT_BUF_N 13 GND 14 L...

Page 114: ...r support of several storage device options This section provides a functional overview and pin out of each connector 7 3 1 SATA 6Gbps Connectors The server board includes two 7 pin SATA connectors capable of transfer rates of up to 6Gbps The following table provides the pin out for both connectors Table 19 SATA 6Gbps Connector Pin out Pin Signal Name 1 GND 2 SATA_TX_P 3 SATA_TX_N 4 GND 5 SATA_RX_...

Page 115: ...e pin out for each connector Table 21 Mini SAS HD Connectors for SAS 12Gbps Pin out Pin Signal Name Pin Signal Name 1A1 TP_SAS1_BACKPLANE_TYPE 2A1 TP_SAS0_BACKPLANE_TYPE 1B1 GND 2B1 GND 1C1 SGPIO_SSATA_DATAOUT0_R1 2C1 SGPIO_SATA_DATAOUT0_R1 1D1 SGPIO_DATAIN 2D1 SGPIO_DATAIN 1A2 SGPIO_SSATA_CLOCK_R1 2A2 SGPIO_SATA_CLOCK_R1 1B2 SGPIO_SSATA_LOAD_R1 2B2 SGPIO_SATA_LOAD_R1 1C2 GND 2C2 GND 1D2 PD_SAS1_C...

Page 116: ... 3 6 Internal eUSB SSD Header The server board includes one 10 pin internal eUSB header with an intended usage of supporting USB SSD devices The following table provides the pin out for this connector Table 25 eUSB SSD Header Pin out Pin Signal Name Pin Signal Name 1 5V 2 NC 3 USB2_PCH_P12_DN 4 NC 5 USB2_PCH_P12_DP 6 NC 7 GND 8 NC 9 Key 10 LED_HDD_ACT_ZEPHER_N 7 3 7 M 2 NGFF Header The server boar...

Page 117: ...38 DEVSLP 1 0 3 3v 37 N C 36 N C 35 N C 34 N C 33 GND 32 N C 31 N C 30 N C 29 N C 28 N C 27 GND 26 N C 25 N C 24 N C 23 N C 22 N C 21 GND 20 N C 19 N C 18 3 3v 17 N C 16 3 3v 15 GND 14 3 3v 13 N C 12 3 3v 11 N C 10 DAS DSS O OD 9 GND 8 N C 7 N C 6 N C 5 N C 4 3 3v 3 GND 2 3 3v 1 GND 7 4 Management and Security Connectors 7 4 1 RMM4 Lite Connector A 7 pin Intel RMM4 Lite connector is included on th...

Page 118: ...CLK_33M_TPM 11 LPC_LAD 3 12 GND 13 GND 14 LPC_LAD 2 7 4 3 PMBus Connector Table 29 PMBus Connector Pin out Pin Signal Name 1 SMB_PMBUS_CLK_R 2 SMB_PMBUS_DATA_R 3 IRQ_SML1_PMBUS_ALERT_RC_N 4 GND 5 P3V3 7 4 4 Chassis Intrusion Header The server board includes a 2 pin chassis intrusion header which can be used when the chassis is configured with a chassis intrusion switch The header has the following...

Page 119: ...M is 25000 7 5 1 System FAN Connectors The six system cooling fan connectors near the front edge of the board are 6 pin connectors the one system cooling fan connector near the edge of the board is a 4 pin connector The following table provides the pin out for all system fan connectors Table 32 6 pin System FAN Connector Pin out Pin Signal Name 1 GND 2 12V 3 TACH 4 PWM 5 PRSNT 6 FAULT Table 33 4 p...

Page 120: ...one internal DH 10 serial port connector Table 35 Serial Port B Connector Pin out Pin Signal Name Pin Signal Name 1 SPA_DCD 2 SPA_DSR 3 SPA_SIN 4 SPA_RTS 5 SPA_SOUT_N 6 SPA_CTS 7 SPA_DTR 8 SPA_RI 9 GND 7 6 2 Video Connector The following table details the pin out definition of the external VGA connector Table 36 Video Connector Pin out Pin Signal Name 1 CRT_RED 2 CRT_GREEN 3 CRT_BLUE 4 N C 5 GND 6...

Page 121: ... and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non operating limits 7 7 PCIe Riser Slot The following table provides the pin out for PCIe slot 6 as a rise...

Page 122: ...O PERP2 B25 GND GND A26 O PERN2 B26 GND GND A27 GND GND B27 I PETP3 A28 GND GND B28 I PETN3 A29 O PERP3 B29 GND GND A30 O PERN3 B30 PWR P3V3 RSVD A31 GND GND B31 O PD via 4 75Kohm PRNST2_N A32 I REFCLKP_2 RSVD B32 GND GND A33 I REFCLKN_2 RSVD B33 I PETP4 A34 GND GND B34 I PETN4 A35 O PERP4 B35 GND GND A36 O PERN4 B36 GND GND A37 GND GND B37 I PETP5 A38 GND GND B38 I PETN5 A39 O PERP5 B39 GND GND A...

Page 123: ...ERP12 B68 GND GND A69 O PERN12 B69 GND GND A70 GND GND B70 I PETP13 A71 GND GND B71 I PETN13 A72 O PERP13 B72 GND GND A73 O PERN13 B73 GND GND A74 GND GND B74 I PETP14 A75 GND GND B75 I PETN14 A76 O PERP14 B76 GND GND A77 O PERN14 B77 GND GND A78 GND GND B78 I PETP15 A79 GND GND B79 I PETN15 A80 O PERP15 B80 GND GND A81 O PERN15 B81 I NC PRSNT2_N A82 GND GND B82 I NC RSVD PCIe riser slot reuses th...

Page 124: ...ies to standard PCIe slot as well Reuse Pin B17 as MUX_RST_N Reuse Pin B48 A50 B31 as LINK_WIDTH_ID Reuse A32 A33 as additional PCIe Clocks to the 2nd slot on the risers NOTES The 3rd REFCLK is not used LINK_WIDTH_ID2 is not used on slot 6 which is pulled to GND via a 4 75Kohm resistor For pin B12 it is connected to system throttling signal to throttle input for Xeon Phi ...

Page 125: ...s System Results BIOS Recovery 1 2 Pins 1 2 should be connected for normal system operation Default 2 3 The main system BIOS does not boot with pins 2 3 connected The system only boots from EFI bootable recovery media with a recovery BIOS image present BIOS Default that is CMOS Clear 1 2 These pins should have a jumper in place for normal system operation Default 2 3 If pins 2 3 are connected when...

Page 126: ...en the server chassis For instructions see your server chassis documentation 3 Move jumper from the default operating position covering pins 1 and 2 to the reset clear position covering pins 2 and 3 4 Wait five seconds 5 Move the jumper back to the default position covering pins 1 and 2 6 Close the server chassis 7 Install AC power cord 8 Power up the server and access the BIOS setup utility by F2...

Page 127: ...emove the system top cover and move the Password Clear jumper back to the default operating position covering pins 1 and 2 9 Reinstall the system top cover and reattach the AC power cords 10 Power up the server The password is now cleared and can be reset by going into the BIOS setup 8 2 Integrated BMC Force Update Procedure When performing the standard Integrated BMC firmware update procedure the...

Page 128: ...dard firmware update process fails This jumper should remain in the default disabled position when the server is running normally 8 3 ME Force Update Jumper When the ME Firmware Force Update jumper is moved from its default position the ME is forced to operate in a reduced minimal operating capacity This jumper should only be used if the ME firmware has gotten corrupted and requires re installatio...

Page 129: ...s 3 Remove the system top cover 4 Move the BIOS Recovery jumper from the default operating position covering pins 1 and 2 to the BIOS Recovery position covering pins 2 and 3 5 Reinstall the system top cover and reattach the AC power cords 6 Power on the system 7 The system will automatically boot to the EFI shell Update the BIOS using the standard BIOS update instructions provided with the system ...

Page 130: ...nd function of each LED on the server boards 9 1 5 volt Stand by LED Several server management features of these server boards require a 5 V stand by voltage supplied from the power supply The features and components that require this voltage must be present when the system is powered down The LED is illuminated when AC power is applied to the platform and 5 V stand by voltage is supplied to the s...

Page 131: ... Family TPS Intel Light Guided Diagnostics Revision 2 4 117 9 2 Fan Fault LEDs Fan fault LEDs are present for the two CPU fans The fan fault LEDs illuminate when the corresponding fan has fault Figure 23 Fan Fault LED s Location ...

Page 132: ... 9 3 DIMM Fault LEDs The server board provides memory fault LED for each DIMM socket These LEDs are located as shown in the following figure The DIMM fault LED illuminates when the corresponding DIMM slot has memory installed and a memory error occurs Figure 24 DIMM Fault LED s Location ...

Page 133: ... 3 4 5 6 MSB POST Code Diagnostic LEDs Figure 25 Location of System Status System ID and POST Code Diagnostic LEDs 9 4 1 System ID LED You can illuminate the blue System ID LED using either of the following two mechanisms By pressing the System ID Button on the system front control panel the ID LED displays a solid blue color until the button is pressed again By issuing the appropriate hex IPMI Ch...

Page 134: ...nstalled 6 Correctable Errors over a threshold and migrating to a spare DIMM memory sparing This indicates that the user no longer has spared DIMMs indicating a redundancy lost condition Corresponding DIMM LED lit 7 In mirrored configuration when memory mirroring takes place and system loses memory redundancy 8 Battery failure 9 BMC executing in uBoot Indicated by Chassis ID blinking at Blinking a...

Page 135: ...C FW images are bad Chassis ID shows blue solid on for this condition 13 240VA fault Off N A Not ready AC power off Note When the server is powered down transitions to the DC off state or S5 the BMC is still on standby power and retains the sensor and front panel status LED state established before the power down event If the system status is normal when the system is powered down the LED is in a ...

Page 136: ...ion used in an Intel Server Chassis The intent of this section is to provide customers with a guide to assist in defining and or selecting a power supply for custom server platform designs that utilize the server board detailed in this document 10 2 750 W Power Supply This specification defines a 750W redundant power supply that supports server systems This power supply has 2 outputs 12V and 12V s...

Page 137: ...A13 12V B13 12V A14 12V B14 12V A15 12V B15 12V A16 12V B16 12V A17 12V B17 12V A18 12V B18 12V A19 PMBus SDA B19 A0 SMBus address A20 PMBus SCL B20 A1 SMBus address A21 PSON B21 12V stby A22 SMBAlert B22 Cold Redundancy Bus A23 Return Sense B23 12V load share bus A24 12V remote Sense B24 No Connect A25 PWOK B25 Compatibility Check pin 10 2 1 2 Handle Retention The power supply has a handle to ass...

Page 138: ...power AMBER Power supply warning events where the power supply continues to operate high temp high power high current slow fan 1Hz Blink Amber Power supply critical event causing a shutdown failure OCP OVP Fan Fail AMBER Power supply FW updating 2Hz Blink GREEN 10 2 1 4 Temperature Requirements The power supply operates within all specified limits over the Top temperature range All airflow passes ...

Page 139: ... 100 Load Power factor 0 65 0 80 0 90 0 95 Tested at 230VAC 50Hz and 60Hz and 115VAC 60Hz Tested according to Generalized Internal Power Supply Efficiency Testing Protocol Rev 6 4 3 This is posted at http efficientpowersupplies epri com methods asp 10 2 2 2 AC Inlet Connector The AC input connector is an IEC 320 C 14 power inlet This inlet is rated for 10A 250VAC 10 2 2 3 AC Input Voltage Specific...

Page 140: ... Fuse The power supply has one line fused in the single line fuse on the line Hot wire of the AC input The line fusing is acceptable for all safety agency requirements The input is a slow blow type AC inrush current does not cause the AC line fuse to blow under any conditions All protection circuits in the power supply does not cause the AC fuse to blow unless a component in the power supply has f...

Page 141: ...10 Output shall be loaded according to the proportional loading method defined by 80 Plus in Generalized Internal Power Supply Efficiency Testing Protocol Rev 6 4 3 This is posted at http efficientpowersupplies epri com methods asp Table 49 Silver Efficiency Requirement Loading 100 of Maximum 50 of Maximum 20 of Maximum 10 of Maximum Minimum Efficiency 91 94 90 82 The power supply passes with enou...

Page 142: ...ty cycles ranging from 10 90 The load transient repetition rate is only a test specification The step load may occur anywhere within the minimum load to the maximum load conditions Table 52 Transient Load Requirements Output Step Load Size See note 2 Load Slew Rate Test Capacitive Load 12VSB 1 0A 0 25 A µsec 20 µF 12V 60 of max load 0 25 A µsec 2000 µF Note For dynamic condition 12V min loading is...

Page 143: ...hall use a FET probe such as Tektronix model P6046 or equivalent 10 2 4 9 Hot Swap Requirements Hot swapping a power supply is the process of inserting and extracting a power supply from an operating power system During this process the output voltages remains within the limits with the capacitive load specified The hot swap test is conducted when the system is operating under static dynamic and z...

Page 144: ...is test the probe clips and capacitors should be located close to the load 10 2 4 12 Timing Requirements These are the timing requirements for the power supply operation The output voltages must rise from 10 to within regulation limits Tvout_rise within 5 to 70ms For 12VSB it is allowed to rise from 1 0 to 25ms All outputs must rise monotonically Table below shows the timing requirements for the p...

Page 145: ...om 12VSB being in regulation to O Ps being in regulation at AC turn on 50 1000 ms T12VSB_holdup Time the 12VSB output voltage stays within regulation after loss of AC 70 ms The 12VSBoutput voltage rise time shall be from 1 0ms to 25ms AC Input Vout PWOK 12Vsb PSON Tsb_on_delay TAC_on_delay Tpwok_on Tvout_holdup Tpwok_holdup Tpson_on_delay Tsb_on_delay Tpwok_on Tpwok_off Tpwok_off Tpson_pwok Tpwok_...

Page 146: ...nectors The voltage does not exceed the maximum levels when measured at the power connectors of the power supply connector during any single point of fail The voltage does not trip any lower than the minimum levels when measured at the power connector 12VSB will be auto recovered after removing OVP limit Table 57 Over Voltage Protection OVP Limits Output voltage Min v Max v 12V 13 3 14 5 12VSB 13 ...

Page 147: ...h or Open OFF MIN MAX Logic level low power supply ON 0V 1 0V Logic level high power supply OFF 2 0V 3 46V Source current Vpson low 4mA Power up delay Tpson_on_delay 5msec 400msec PWOK delay Tpson_pwok 50msec Figure 29 PSON Required Signal Characteristic 10 2 6 2 PWOK Power OK Output Signal PWOK is a power OK signal and will be pulled HIGH by the power supply to indicate that all the outputs are w...

Page 148: ...his signal indicates that the power supply is experiencing a problem that the user should investigate This shall be asserted due to Critical events or Warning events The signal shall be activated in case the critical component temperature reaches a warning threshold general failure over current over voltage under voltage or fan failure This signal may also indicate the power supply is reaching its...

Page 149: ...atile memory when a critical event shuts down the power supply This data is accessible by the SMBus interface with an external source providing power to the 12Vstby output Refer to the Intel Common Hardware and Firmware Requirements for CRPS Power Supplier for detailed requirements 10 2 9 Firmware Uploader The power supply has the capability to update its firmware by the PMBus interface while it i...

Page 150: ... to the output connector of the PS and it contains 3 DC DC power converters to produce other required voltages 3 3VDC 5VDC and 5V standby along with additional over current protection circuit for the 12V rails The Intel Server Chassis P4304XXMUXX family includes this PDB 10 3 1 Mechanical Overview Figure 30 Outline Drawing 10 3 1 1 Airflow Requirements The power distribution board shall get enough...

Page 151: ...range 0 50 C Tnon op Non operating temperature range 40 70 C 10 3 1 4 Efficiency Each DC DC converter shall have a minimum efficiency of 85 at 50 100 loads and over 12V line voltage range and over temperature and humidity range 10 3 2 DC Output Specification 10 3 2 1 Input Connector Power Distribution Mating Connector The power distribution provides two power pin a card edge output connection for ...

Page 152: ...turn Sense B23 12V load share A24 12V remote Sense B24 No Connect A25 PWOK B25 Compatibility Pin The compatibility Pin is used for soft compatibility check The two compatibility pins are connected directly 10 3 2 2 Output Wire Harness The power distribution board has a wire harness output with the following connectors Listed or recognized component appliance wiring material AVLV2 CN rated min 85 C...

Page 153: ...on Connector only no cable N a P12 4 Aux baseboard power connector for PCIe slots Connector only no cable N a P13 4 GFX card aux connectors Connector only no cable N a P14 4 Connector only no cable N a P15 4 Connector only no cable N a P16 4 10 3 2 2 1 Baseboard Power Connector P1 Connector housing 24 pin Molex Mini Fit Jr 39 01 2245 or equivalent Contact Molex Mini Fit HCS Plus Female Crimp 44476...

Page 154: ...nector P3 Connector housing 8 pin Molex 39 01 2080 or equivalent Contact Molex Mini Fit HCS Plus Female Crimp 44476 or equivalent Table 66 P1 Processor Power Connector Pin Signal 18 AWG color Pin Signal 18 AWG Color 1 COM Black 5 12V1 Brown 2 COM Black 6 12V1 Brown 3 COM Black 7 12V1 Brown 4 COM Black 8 12V1 Brown 10 3 2 2 4 Power Signal Connector P4 Connector housing 5 pin Molex 50 57 9405 or equ...

Page 155: ...tors P7 P8 P9 P10 Connector housing Molex 0015 24 4048 or equivalent Contact Molex 0002 08 1201 or equivalent Table 70 P8 P9 Legacy Peripheral Power Connectors Pin Signal 18 AWG Color 1 12V3 Green 2 COM Black 3 COM Black 4 5 VDC Red Table 71 P7 P10 P11 Legacy Peripheral Power Connectors Pin Signal 18 AWG Color 1 12V3 Green 2 COM Black 3 COM Black 4 5 VDC Red 10 3 2 2 7 SATA 1x5 Peripheral Power Co...

Page 156: ...on Power supply main 12V On PDB On PDB 12V 3 3V P20 1x5 signal connector P20 1x5 signal connector 12V 5V On PDB On PDB 12V 12V none none 12Vstby 5Vstby none none Table 74 Remote Sense Requirements Characteristic Requirement 3 3V remote sense input impedance 200Ω measure from 3 3V on P1 2x12 connector to 3 3V sense on P20 1x5 signal connector 3 3V remote sense drop 200mV remote sense must be able t...

Page 157: ...following table shows the hard drive configuration options using the defined power connectors In some cases additional converter or Y cables are needed Table 76 Hard Drive 12V Rail Configuration Options P8 P9 P10 P11 P5 P6 P7 1x4 1x4 1x4 1x4 1x5 1x5 1x4 18 3 x 2 5 8xHDD BP HDD1 8 x 2 5 HDD2 8 x 2 5 N a N a N a N a HDD3 8 x 2 5 2 x 3 5 4xHDD BP HDD1 4x3 5 HDD1 4x3 5 peripheral bay 1 x 3 5 8xHDD BP ...

Page 158: ...peak ripple noise specified in Table 82 The 3 3V and 5V outputs are measured at the remote sense point all other voltages measured at the output harness connectors Table 79 Voltage Regulation Limits Converter Output Tolerance Min Nom Max Units 3 3VDC 4 5 3 20 3 30 3 46 VDC 5VDC 4 5 4 80 5 00 5 25 VDC 5Vstby 4 5 4 80 5 00 5 25 VDC 10 3 2 10 DC DC Converters Dynamic Loading The output voltages remai...

Page 159: ...bility with local sensing through the submission of Bode plots Closed loop stability must be ensured at the maximum and minimum loads as applicable 10 3 2 13 Common Mode Noise The Common Mode noise on any output does not exceed 350mV pk pk over the frequency band of 10Hz to 20MHz The measurement shall be made across a 100Ω resistor between each of DC outputs including ground at the DC power connec...

Page 160: ... main output 3 3V 5V 12V and 5Vstby 1 0 20 msec The main DC DC converters 3 3V 5V 12V shall be in regulation limits within this time after the 12V input has reached 11 4V 20 msec The main DC DC converters 3 3V 5V 12V must drop below regulation limits within this time after the 12V input has dropped below 11 4V 20 msec The 5Vstby converter shall be in regulation limits within this time after the 12...

Page 161: ...xceeded The limits are listed in below table 12V and 5VSB is protected under over current or shorted conditions so that no damage can occur to the power supply Auto recovery feature is a requirement on 5VSB rail Table 84 PDB Over Current Protection Limits 240VA Protection Output Voltage Min OCP Trip Limits Max OCP Trip Limits Usage Connectors 3 3V 27A 32A PCIe Misc P1 P5 P6 5V 27A 32A PCIe HDD Mis...

Page 162: ...below depending upon the motherboard s pull up voltage Refer to the CRPS Power Supply Specification for signal details Table 86 System PWOK Requirements Motherboard Pull up Voltage MIN Resistance Value ohms 5V 10K 3 3V 6 8K 10 3 5 PSON Signal The PDB connects the power supplies PSON signals together and connect them to the PSON signal on P1 Refer to the CRPS Power Supply Specification for signal d...

Page 163: ...om Shock and vibration packaged ISTA International Safe Transit Association Test Procedure 3A Note 1 Chassis design must provide proper airflow to avoid exceeding the processor maximum case temperature Disclaimer Note Intel ensures the unpackaged server board and system meet the shock requirement mentioned above through its own chassis development and system configuration It is the responsibility ...

Page 164: ...mits 11 2 MTBF The following is the calculated Mean Time Between Failures MTBF 40 C ambient air These values are derived using a historical failure rate and multiplied by factors for application electrical and or thermal stress and for device maturity You should view MTBF estimates as reference numbers only Calculation Model Telcordia Issue 2 method I case 3 Operating Temperature Server in 40 C am...

Page 165: ...channels For example a two DIMM configuration performs better than a one DIMM configuration In a two DIMM configuration with two CPUs installed DIMMs should be installed in DIMM sockets A1 and E1 The Intel Remote Management Module 4 Intel RMM4 connector is not compatible with any previous versions of the Intel Remote Management Module Product Order Code AXXRMM AXXRMM2 and AXXRMM3 Clear the CMOS wi...

Page 166: ... Intel Server Board S2600CW can be used inside the Intel Server Chassis P4000M family Table 90 Compatible Intel Server Chassis Chassis Name System Fans Storage Drives Power Supply P4304XXMFEN2 Two fixed Fans Fixed HDD trays One 550 W Non redundant P4304XXMUXX Five redundant Fans Fixed HDD trays N A Compatible with 750 W or 1600 W Redundant PSUs ...

Page 167: ...m the Event Reading Type Code Ranges and the Generic Event Reading Type Code tables in the Intelligent Platform Management Interface Specification Second Generation Version 2 0 Digital sensors are specific type of discrete sensors that only have two states Event Thresholds Triggers The following event thresholds are supported for threshold type sensors u l nr c nc upper non recoverable upper criti...

Page 168: ... sensors can be done manually or automatically This column indicates the type supported by the sensor The following abbreviations are used in the comment column to describe a sensor A Auto rearm M Manual rearm I Rearm by init agent Default Hysteresis The hysteresis setting applies to all thresholds of the sensor This column provides the count of hysteresis for the sensor which can be 1 or 2 positi...

Page 169: ...ent Offset Triggers Contrib To System Status Assert De assert Readab le Value Offsets Event Data Rearm Stand by Power Unit Status Pwr Unit Status 01h All Power Unit 09h Sensor Specific 6Fh 00 Power down OK As and De Trig Offset A X 02 240 VA power down Fatal 04 A C lost OK 05 Soft power control failure Fatal 06 Power unit failure Power Unit Redundancy1 Pwr Unit Redund 02h Chassis specific Power Un...

Page 170: ...ower cycle 08 Timer interrupt Physical Security Physical Scrty 04h Chassis Intrusion is chassis specific Physical Security 05h Sensor Specific 6Fh 00 Chassis intrusion Degraded OK As and De Trig Offset A X 04 LAN leash lost FP Interrupt FP NMI Diag Int 05h Chassis specific Critical Interrupt 13h Sensor Specific 6Fh 00 Front panel NMI diagnostic interrupt OK As Trig Offset A QPI Correctable Event Q...

Page 171: ... 00 Power Button 02 Reset Button OK AS _ Trig Offset A X BMC Watchdog 0Ah All Mgmt System Health 28h Digital Discrete 03h 01 State Asserted Degraded As Trig Offset A Voltage Regulator Watchdog VR Watchdog 0Bh All Voltage 02h Digital Discrete 03h 01 State Asserted Fatal As and De Trig Offset M X Fan Redundancy1 Fan Redundancy 0Ch Chassis specific Fan 04h Generic 0Bh 00 Fully redundant OK As and De ...

Page 172: ...resence 0Eh Platform specific Module Board 15h Digital Discrete 08h 01 Inserted Present OK As and De Trig Offset M SAS Module Presence SAS Mod Presence 0Fh Platform specific Module Board 15h Digital Discrete 08h 01 Inserted Present OK As and De Trig Offset M X BMC Firmware Health BMC FW Health 10h All Mgmt Health 28h Sensor Specific 6Fh 04 Sensor Failure Degraded As Trig Offset A X System Airflow ...

Page 173: ...orm specific Temperature 01h Threshold 01h u l c nc nc Degraded c Non fatal As and De Analog R T A X PCI Riser 3 Temperature PCI Riser 3 Temp 17h Platform specific Temperature 01h Threshold 01h u l c nc nc Degraded c Non fatal As and De Analog R T A X PCI Riser 4 Temperature PCI Riser 4 Temp 18h Platform specific Temperature 01h Threshold 01h u l c nc nc Degraded c Non fatal As and De Analog R T A...

Page 174: ...log R T A X Baseboard Temperature 4 Platform Specific 25h Platform specific Temperature 01h Threshold 01h u l c nc nc Degraded c Non fatal As and De Analog R T A X IO Module Temperature I O Mod Temp 26h Platform specific Temperature 01h Threshold 01h u l c nc nc Degraded c Non fatal As and De Analog R T A X PCI Riser 1 Temperature PCI Riser 1 Temp 27h Platform specific Temperature 01h Threshold 01...

Page 175: ...aded c Non fatal As and De Analog R T A X Exit Air Temperature Exit Air Temp 2Eh Chassis and Platform Specific Temperature 01h Threshold 01h This sensor does not generate any events nc Degraded c Non fatal As and De Analog R T A X Network Interface Controller Temperature LAN NIC Temp 2Fh All Temperature 01h Threshold 01h u l c nc nc Degraded c Non fatal As and De Analog R T A X Fan Tachometer Sens...

Page 176: ... Supply 2 AC Power Input PS2 Power In 55h Chassis specific Other Units 0Bh Threshold 01h u c nc nc Degraded c Non fatal As and De Analog R T A X Power Supply 1 12V of Maximum Current Output PS1 Curr Out 58h Chassis specific Current 03h Threshold 01h u c nc nc Degraded c Non fatal As and De Analog R T A X Power Supply 2 12V of Maximum Current Output PS2 Curr Out 59h Chassis specific Current 03h Thr...

Page 177: ...cific 6Fh 01 Thermal trip Fatal As and De Trig Offset M X 07 Presence OK Processor 4 Status P4 Status 73h Platform specific Processor 07h Sensor Specific 6Fh 01 Thermal trip Fatal As and De Trig Offset M X 07 Presence OK Processor 1 Thermal Margin P1 Therm Margin 74h All Temperature 01h Threshold 01h Analog R T A Processor 2 Thermal Margin P2 Therm Margin 75h All Temperature 01h Threshold 01h Anal...

Page 178: ...set A Processor ERR2 Timeout CPU ERR2 7Ch All Processor 07h Digital Discrete 03h 01 State Asserted Fatal As and De Trig Offset A Catastrophic Error CATERR 80h All Processor 07h Digital Discrete 03h 01 State Asserted Fatal As and De Trig Offset M MTM Level Change MTM Lvl Change 81h All Mgmt Health 28h Digital Discrete 03h 01 State Asserted As and De Trig Offset A Processor Population Fault CPU Miss...

Page 179: ...r Temperature VRD Hot 90h All Temperature 01h Digital Discrete 05h 01 Limit exceeded Non fatal As and De Trig Offset A Power Supply 1 Fan Tachometer 1 PS1 Fan Tach 1 A0h Chassis specific Fan 04h Generic digital discrete 03h 01 State Asserted Non fatal As and De Trig Offset M Power Supply 1 Fan Tachometer 2 PS1 Fan Tach 2 A1h Chassis specific Fan 04h Generic digital discrete 03h 01 State Asserted N...

Page 180: ...perature 01h Threshold 01h u c nc nc Degraded c Non fatal As and De Analog R T A Processor 1 DIMM Aggregate Thermal Margin 2 P1 DIMM Thrm Mrgn2 B1h All Temperature 01h Threshold 01h u c nc nc Degraded c Non fatal As and De Analog R T A Processor 2 DIMM Aggregate Thermal Margin 1 P2 DIMM Thrm Mrgn1 B2h All Temperature 01h Threshold 01h u c nc nc Degraded c Non fatal As and De Analog R T A Processor...

Page 181: ...gital discrete 03h 01 State Asserted Non fatal As and De Trig Offset A Fan Tachometer Sensors Chassis specific sensor names BAh BFh Chassis and Platform Specific Fan 04h Threshold 01h l c nc nc Degraded c Non fatal2 As and De Analog R T M Processor 1 DIMM Thermal Trip P1 Mem Thrm Trip C0h All Memory 0Ch Sensor Specific 6Fh 0A Critical overtemperature Fatal As and De Trig Offset M Processor 2 DIMM ...

Page 182: ...gn 1 C8h Platform Specific Temperature 01h Threshold 01h Analog R T A Global Aggregate Temperature Margin 2 Agg Therm Mrgn 2 C9h Platform Specific Temperature 01h Threshold 01h Analog R T A Global Aggregate Temperature Margin 3 Agg Therm Mrgn 3 CAh Platform Specific Temperature 01h Threshold 01h Analog R T A Global Aggregate Temperature Margin 4 Agg Therm Mrgn 4 CBh Platform Specific Temperature 0...

Page 183: ...Degraded c Non fatal As and De Analog R T A Hot swap Backplane 4 Temperature HSBP 4 Temp E0h Chassis specific Temperature 01h Threshold 01h u l c nc nc Degraded c Non fatal As and De Analog R T A X Rear Hard Disk Drive 0 1 Status Rear HDD 0 1 Stat E2h E3h Chassis specific Drive Slot 0Dh Sensor Specific 6Fh 00 Drive Presence OK As and De Trig Offset A X 01 Drive Fault Degraded 07 Rebuild Remap in p...

Page 184: ...Appendix C BMC Sensor Tables Intel Server Board S2600CW Family TPS 170 Revision 2 4 ...

Page 185: ...tion of BMC channels assignments Channel ID Interface Supports Sessions 0 Primary IPMB No 1 LAN1 Yes 2 LAN2 Yes 3 LAN3 1 Provided by the Intel Remote Management Module 4 Yes 4 Serial COM2 terminal mode only Yes 5 USB No 6 SMLink1 IPMB connection to Node Manager Bridged through BMC No 7 SMM No 8 0Dh Reserved 0Eh Self 2 0Fh SMS Receive Message Queue No Notes 1 Optional HW supported by the server sys...

Page 186: ...em Fan 1 30h Fan 1 Present 40h System Fan 2 31h Fan 2 Present 41h System Fan 3 32h Fan 3 Present 42h System Fan 4 33h Fan 4 Present 43h System Fan 5 34h Fan 5 Present 44h Hot plug Fan Support Supported on Intel Server Chassis P4000 Redundant Union Peak Medium only Fan Redundancy Support Supported on Intel Server Chassis P4000 Redundant Union Peak Medium only Fan Domain Definition Chassis Fan Domai...

Page 187: ...t Air Temp 2Eh P1 DTS Therm Mgn 83h P2 DTS Therm Mgn 84h MIC 1 Margin C4h MIC 2 Margin C5h MIC 3 Margin C6h System Fan 2 31h 2 DIMM Thrm Mrgn 1 B0h DIMM Thrm Mrgn 2 B1h DIMM Thrm Mrgn 3 B2h DIMM Thrm Mrgn 4 B3h SAS IOC Temp D6h MEM EFVRD Temp 24h MEM VRM Temp D5h P1 VRD Temp 25h HSBP 1 Temp 29h Exit Air Temp 2Eh P1 DTS Therm Mgn 83h P2 DTS Therm Mgn 84h MIC 1 Margin C4h MIC 2 Margin C5h MIC 3 Marg...

Page 188: ...5h P1 VRD Temp 25h HSBP 1 Temp 29h Exit Air Temp 2Eh P1 DTS Therm Mgn 83h P2 DTS Therm Mgn 84h MIC 1 Margin C4h MIC 2 Margin C5h MIC 3 Margin C6h System Fan 5 34h 5 PS1 Temperature 5Ch PS2 Temperature 5Dh Power supply fans P4304XXMFEN2 0 DIMM Thrm Mrgn 1 B0h DIMM Thrm Mrgn 2 B1h DIMM Thrm Mrgn 3 B2h DIMM Thrm Mrgn 4 B3h LAN BMC Temp 23h HSBP 1 Temp 29h SSB Temp 22h LAN NIC Temp 2Fh Exit Air Temp 2...

Page 189: ...XX8X25PCIHSBP 8 bay 2 5 HDD SAS Only FXX8X25S3HSBP Intel Server Chassis P4304XXMFEN2 4 bay 3 5 HDD FUP4X35S3HSBP 8 bay 2 5 HDD Combo FXX8X25PCIHSBP 8 bay 2 5 HDD SAS Only FXX8X25S3HSBP Power Unit Redundancy Support Intel Server Chassis P4304XXMUXX Redundant Fans only for Intel Server Chassis Intel Server Chassis P4304XXMUXX Fan Fault LED Support Fan fault LEDs are available on the baseboard and on...

Page 190: ...rver board To assist in troubleshooting a system hang during the POST process the Diagnostic LEDs can be used to identify the last POST process that was executed Each POST code is represented by a sequence of eight amber diagnostic LEDs The POST codes are divided into two groups of LEDs as shown in the figure below The diagnostic LED 7 is labeled as MSB and the diagnostic LED 0 is labeled as LSB F...

Page 191: ...a list of all POST progress codes Table 93 POST Progress Codes Progress Code Description SEC Phase 0x01 First Post code after CPU reset 0x02 Microcode load begin 0x03 CRAM initialization begin 0x04 PEI Cache When Disabled 0x05 SEC Core At Power On Begin 0x06 Early CPU initialization during SEC phase QPI RC Fully leverage without platform change 0xA1 Collect info such as SBSP Boot Mode Reset type e...

Page 192: ...during SEC phase 0x08 Early NB initialization during SEC phase 0x09 End of SEC phase 0x0E Microcode Not Found 0x0F Microcode Not Loaded PEI Phase 0x10 PEI Core 0x11 CPU PEIM 0x15 NB PEIM 0x19 SB PEIM MRC Progress Codes At this point the MRC Progress Code sequence ix executed See Table 94 0x31 Memory Installed 0x32 CPU PEIM CPU Init 0x33 CPU PEIM Cache Init 0x4F DEX IPL Started DXE Phase 0x60 DXE C...

Page 193: ...nit 0x6A DXE NB SMM Init 0x70 DXE SB Init 0x71 DXE SB SMM Init 0x72 DXE SB devices Init 0x78 DXE ACPI Init 0x79 DXE CSM Init 0x80 DXE BDS Started 0x81 DXE BDS connect drivers 0x82 DXE PCI Bus begin 0x83 DXE PCI Bus HPC Init 0x84 DXE PCI Bus Enumeration 0x85 DXE PCI Bus resource requested 0x86 DXE PCI Bus assign resource 0x87 DXE CON_OUT connect 0x88 DXE CON_IN connect 0x89 DXE SIO Init 0x8A DXE US...

Page 194: ...CSI begin 0x96 DXE SCSI reset 0x97 DXE SCSI detect 0x98 DXE SCSI enable 0x99 DXE verifying SETUP password 0x9B DXE SETUP start 0x9C DXE SETUP input wait 0x9D DXE Ready to Boot 0x9E DXE Legacy Boot 0x9F DXE Exit Boot Services 0xC0 RT Set Virtual Address Map Begin 0xC2 DXE Legacy Option ROM Init 0xC3 DXE Reset system 0xC4 DXE USB Hot plug 0xC5 DXE PCI BUS Hot plug 0xC6 DXE NVRAM cleanup 0xC7 DXE ACP...

Page 195: ...MRC Progress Codes are displays to the Diagnostic LEDs that show the execution point in the MRC operational path at each step S3 Resume 0x40 S3 Resume PEIM S3 started 0x41 S3 Resume PEIM S3 boot script 0x42 S3 Resume PEIM S3 Video Repost 0x43 S3 Resume PEIM S3 OS wake BIOS Recovery 0x46 PEIM which detected forced Recovery condition 0x47 PEIM which detected User Recovery condition 0x48 Recovery PEI...

Page 196: ...l level n a 0x B6 Perform the JEDEC defined initialization sequence n a 0x B7 Train DDR4 ranks n a 0x01 Read DQ DQS training 0x02 Receive Enable training 0x03 Write leveling training 0x04 Write DQ DQS training 0x05 DDR Channel training done 0x B8 Initialize CLTT OLTT n a 0x B9 Hardware memory test and init n a 0x BA Execute software memory init n a 0x BB Program memory map and interleaving n a 0x ...

Page 197: ...at causes no operable memory 02h Memory DIMMs on all channels of all sockets are disabled due to hardware memtest error 03h No memory installed All channels are disabled 0xE9 Memory is locked by Intel Trusted Execution Technology and is inaccessible 0xEA DDR4 Channel Training Error 01h Error on read DQ DQS Data Data Strobe Init 02h Error on Receive Enable 03h Error on Write Leveling 04h Error on w...

Page 198: ...BIOS setup does not have any effect on this error Major The message is displayed on the Error Manager screen and an error is logged to the SEL The POST Error Pause option setting in the BIOS setup determines whether the system pauses to the Error Manager for this type of error so the user can take immediate corrective action or the system continues booting Fatal The system halts during post at a b...

Page 199: ...ller failed self test Major 8305 Hot Swap Controller failure Major 83A0 Management Engine ME failed Selftest Major 83A1 Management Engine ME Failed to respond Major 84F2 Baseboard management controller failed to respond Major 84F3 Baseboard management controller in update mode Major 84F4 Sensor data record empty Major 84FF System event log full Minor 8500 Memory component could not be configured i...

Page 200: ...tion Major 853C DIMM_J2 failed test initialization Major 853D DIMM_J3 failed test initialization Major 853E DIMM_K1 failed test initialization Major 853F Go to 85C0 DIMM_K2 failed test initialization Major 8540 DIMM_A1 disabled Major 8541 DIMM_A2 disabled Major 8542 DIMM_A3 disabled Major 8543 DIMM_B1 disabled Major 8544 DIMM_B2 disabled Major 8545 DIMM_B3 disabled Major 8546 DIMM_C1 disabled Majo...

Page 201: ...6D DIMM_E2 encountered a Serial Presence Detection SPD failure Major 856E DIMM_E3 encountered a Serial Presence Detection SPD failure Major 856F DIMM_F1 encountered a Serial Presence Detection SPD failure Major 8570 DIMM_F2 encountered a Serial Presence Detection SPD failure Major 8571 DIMM_F3 encountered a Serial Presence Detection SPD failure Major 8572 DIMM_G1 encountered a Serial Presence Dete...

Page 202: ...5D6 DIMM_M3 disabled Major 85D7 DIMM_N1 disabled Major 85D8 DIMM_N2 disabled Major 85D9 DIMM_N3 disabled Major 85DA DIMM_O1 disabled Major 85DB DIMM_O2 disabled Major 85DC DIMM_O3 disabled Major 85DD DIMM_P1 disabled Major 85DE DIMM_P2 disabled Major 85DF DIMM_P3 disabled Major 85E0 DIMM_K3 encountered a Serial Presence Detection SPD failure Major 85E1 DIMM_L1 encountered a Serial Presence Detecti...

Page 203: ...e following table lists the POST error beep codes Prior to system video initialization the BIOS uses these beep codes to inform users on error conditions The beep code is followed by a user visible code on the POST Progress LEDs Table 97 POST Error Beep Codes Beeps Error Message POST Progress Code Description 3 Memory error See Table 93 System halted because a fatal error related to the memory was...

Page 204: ...opout Power unit power unit failure offset 1 5 4 4 Power control fault power good assertion timeout Power unit soft power control failure offset 1 5 1 2 VR Watchdog Timer sensor assertion VR Watchdog Timer 1 5 1 4 The system does not power on or unexpectedly powers off and a power supply unit PSU is present that is an incompatible model with one or more other PSUs in the system PS Status ...

Page 205: ... EEROM None Volatile 16MB U2A1 No X540 flash ROM Volatile 256MB U1A1 No BMC FW SDRAM None Volatile 16MB U7V1 No LSISAS3008 NOR flash None Volatile 64KB U7W2 No LSISAS3008 SBL EEPROM None Volatile 32KB U3H2 No LSISAS3008 nvSRAM or mRAM Component Type Three types of components are on an Intel server board These types are Non volatile Non volatile memory is persistent and is not cleared when power is...

Page 206: ...and are unique and unrelated to operating system passwords The specific components that may contain password data are BIOS The server board BIOS provides the capability to prevent unauthorized users from configuring BIOS settings when a BIOS password is set This password is stored in BIOS flash and is only used to set BIOS configuration access restrictions BMC The server boards support an Intellig...

Page 207: ...rap Processor byte 8 bit quantity CBC Chassis Bridge Controller A microcontroller connected to one or more other CBCs together they bridge the IPMB buses of multiple chassis CEK Common Enabling Kit CHAP Challenge Handshake Authentication Protocol CMOS In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory which normally resides on the server...

Page 208: ... Unit Number MAC Media Access Control MB 1024KB mBMC National Semiconductor PC87431x mini BMC MCH Memory Controller Hub MD2 Message Digest 2 Hashing Algorithm MD5 Message Digest 5 Hashing Algorithm Higher Security ms milliseconds MTTR Memory Tpe Range Register Mux Multiplexor NIC Network Interface Controller NMI Nonmaskable Interrupt NTB Non Transparent Bridge OBF Output Buffer OEM Original Equipm...

Page 209: ...Edge Connector Cartridge SEEPROM Serial Electrically Erasable Programmable Read Only Memory SEL System Event Log SIO Server Input Output SMI Server Management Interrupt SMI is the highest priority nonmaskable interrupt SMM Server Management Mode SMS Server Management Software SNMP Simple Network Management Protocol TBD To Be Determined TIM Thermal Interface Material UART Universal Asynchronous Rec...

Page 210: ...e Specification Version 1 1 02 01 02 Intel Corporation Intel Remote Management Module User s Guide Intel Corporation Alert Standard Format ASF Specification Version 2 0 23 April 2003 2000 2003 Distributed Management Task Force Inc http www dmtf org Intel Server System BIOS External Product Specification for Intel Servers Systems supporting the Intel Xeon processor E5 2600 V3 and V4 product family ...

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