Intel® Server Board S2600CW Functional Architecture
Intel® Server Board S2600CW Family TPS
32
Revision 2.4
Potential Error Cases:
Invalid DIMM (type, organization, speed, size) – If a DIMM is found that is not a type
supported by the system, the following error will be generated: POST Error Code
8501
“DIMM Population Error”, and a “Population Error” Fatal Error Halt
0xED
.
Invalid DIMM Installation – The DIMMs are installed incorrectly on a channel, not
following the “Fill Farthest First” rule (Slot 1 must be filled before Slot 2, Slot 2 before
Slot 3). This will result in a POST Error Code
8501
“DIMM Population Error” with the
channel being disabled, and all DIMMs on the channel will be disabled with a POST
Error Code
854x
“DIMM Disabled” for each. This could also result in a “No usable
memory installed” Fatal Error Halt
0xE8
.
Invalid DIMM Population – A QR RDIMM or a QR LRDIMM in Direct Map mode which is
installed in Slot3 on a 3 DIMM per channel server board is not allowed. This will result
in a POST Error Code
8501
“DIMM Population Error” and a “Population Error” Fatal
Error Halt
0xED
.
Note:
3 QR LRDIMMs on a channel is an acceptable configuration if operating in Rank
Multiplication mode with RM equal to 2 or 4. In this case each QR LRDIMM appears to
be a DR or SR DIMM.
Mixed DIMM Types – A mixture of RDIMMs and/or LRDIMMs is not allowed. A mixture
of LRDIMMs operating in Direct Map mode and Rank Multiplication mode is also not
allowed. This will result in a POST Error Code
8501
“DIMM Population Error” and
“Population Error” Fatal Error Halt
0xED
.
Mixed DIMM Parameters – Within an RDIMM or LRDIMM configuration, mixtures of valid
DIMM technologies, sizes, speeds, latencies, etc., although not supported, will be
initialized and operated on a best efforts basis, if possible.
No usable memory installed – If no enabled and available memory remains in the
system, this will result in a Fatal Error Halt
0xE8
.
3.3.6.3
Channel Training
The Integrated Memory Controller registers are programmed at the controller level and the
memory channel level. Using the DIMM operational parameters, read from the SPD of the
DIMMs on the channel, each channel is trained for optimal data transfer between the
integrated memory controller (IMC) and the DIMMs installed on the given channel.
Potential Error Cases:
Channel Training Error – If the Data/Data Strobe timing on the channel cannot be set
correctly so that the DIMMs can become operational, this results in a momentary Error
Display
0xEA
, and the channel is disabled. All DIMMs on the channel are marked as
disabled, with POST Error Code
854x
“DIMM Disabled” for each. If there are no
populated channels which can be trained correctly, this becomes a Fatal Error Halt
0xEA
.
