xvi
24
●
Crystal Oscillator Circuit is changed.
(Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. is
added.)
●
Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs is changed.
((turning on/off the analog and digital power supplies simultaneously is acceptable) is deleted.)
●
Note on operation during PLL clock mode is changed.
55
Figure 3.1-2 Overview of Software Interrupts is changed.
(ILM : Interrupt level mask register
→
S :Stack flag)
59
Notes is changed.
(
•
ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only. is added.)
(<Additional information> is added.)
63
Figure 3.4-2 Register Saving During Interrupt Processing is changed.
(DPB
→
DTB)
68
Figure 3.5-2 Registers Saved in Stack is changed.
(DPB
→
DTB)
70
Figure 3.6-1 Occurrence and Release of Software Interrupt is changed.
(ILM : Interrupt level mask register
→
S :Stack flag)
78
●
When data transfer continues (when the stop condition is not satisfied) is changed.
((Table 3.8-1 "Execution time when the extended EI
2
OS continues" + Table 3.8-2 "Data transfer compensa-
tion values for extended EI
2
OS execution time") machine cycles
→
((Table 3.8-1 + Table 3.8-2) machine
cycles)
103
Summary of 5.7 Output of the main clock HCLK and HCLKX is changed.
105
CHAPTER 6 CLOCK MODULATOR
Notes is changed.
112
Table 6.3-1 Function of Each Bit of the Clock Modulator Control Register (3/3)
Function of bit1 is changed.
(6 ms
→
6
µ
s)
113
Table 6.3-2 States of the Modulator is changed.
(modulator power on, waiting modulator startup time (> 6 ms)
→
modulator power on, waiting modulator startup time (> 6
µ
s))
114
Figure 6.3-3 Modulation Parameter Register is changed.
(CMPRL (upper)
→
CMPRH (upper))
(XX0000010
B
→
XX000010
B
)
141
Figure 8.2-1 Block Diagram of the Low-power Consumption Control Circuit is changed.
(Osc. stab. wait clear
→
Oscillation stabilization wait time clear)
158
8.7 Status of Pins in Standby Mode and during Reset is added.
175
■
Analog Input Enable Registers
Note is changed.
(ANIN 0 to 7
→
AN0 to AN7)
(ANIN 8 to 14
→
AN8 to AN14)
184
Figure 12.1-1 Watchdog Timer Block Diagram is changed.
187
■
State Transition Diagram of the Watchdog Timer is added.
188
■
Watchdog Counter is changed.
■
Watchdog Stop is changed.
■
Watchdog Deactivation is added.
■
Watchdog Timer Behavior in Stop Mode, Time-base Timer Mode, and Sleep Mode is added.
189
■
Watchdog Timer Behavior at Reset is added.
Reference: Main changes (Rev.2
→
Rev.3)
Page
Changes (For details, refer to main body.)
Summary of Contents for MB90390 Series
Page 2: ......
Page 4: ......
Page 17: ...xiii APPENDIX D List of Interrupt Vectors 690 INDEX 695 ...
Page 18: ...xiv ...
Page 132: ...104 CHAPTER 5 CLOCKS ...
Page 152: ...124 CHAPTER 6 CLOCK MODULATOR ...
Page 210: ...182 CHAPTER 11 TIME BASE TIMER ...
Page 218: ...190 CHAPTER 12 WATCHDOG TIMER ...
Page 264: ...236 CHAPTER 14 16 BIT RELOAD TIMER WITH EVENT COUNT FUNCTION ...
Page 274: ...246 CHAPTER 15 WATCH TIMER ...
Page 306: ...278 CHAPTER 17 DTP EXTERNAL INTERRUPTS ...
Page 338: ...310 CHAPTER 18 8 10 BIT A D CONVERTER ...
Page 364: ...336 CHAPTER 19 UART0 UART1 ...
Page 398: ...370 CHAPTER 20 UART2 UART3 Figure 20 5 2 ORE Set Timing Receive data RDRF ORE ...
Page 432: ...404 CHAPTER 20 UART2 UART3 ...
Page 482: ...454 CHAPTER 22 SERIAL I O ...
Page 560: ...532 CHAPTER 24 STEPPING MOTOR CONTROLLER ...
Page 582: ...554 CHAPTER 27 ROM MIRRORING MODULE ...
Page 632: ...604 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION ...
Page 722: ...694 APPENDIX ...
Page 723: ...695 INDEX The index follows on the next page This is listed in alphabetic order ...
Page 740: ......