Fujitsu MB90390 Series, Hardware Manual, Page: 171 / 740

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CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.3 Low-Power Consumption Mode Control Register (LPMCR)
This register switches to or releases the low-power consumption mode. This register
also sets the number of CPU clock pulses to halt during the CPU intermittent operation
mode.
■
Low-power Consumption Mode Control Register (LPMCR)
Figure 8.3-1 shows the configuration of the low-power consumption mode control register (LPMCR).
Figure 8.3-1 Configuration of the Low-power Consumption Mode Control Register (LPMCR)
Addre ss :
0000A0
H
00011000
B
(CK S CR) S TP S LP
Re-
s erved
S PL R S T TMD CG1 CG0
CG1
0 0
0 cycle s (CPU clock = Re s o u rce clock)
8 cycle s (CPU clock: Re s o u rce clock =1: 3 to 4 a pprox.)
16 cycle s (CPU clock: Re s o u rce clock = 1:5 to 6 a pprox.)
3 2 cycle s (CPU clock: Re s o u rce clock = 1:9 to 10 a pprox.)
0 1
1 0
1 1
CG0 Co u nt b it for CPU clock tempor a ry h a lt cycle
Alw a y s write "0" to thi s b it
Re s erved b it Re s erved
TMD
0 S witche s to the time- bas e timer mode
No ch a nge, no effect on oper a tion
1
Time- bas e timer mode b it
R S T
0 Gener a te s a n intern a l re s et s ign a l of three m a chine cycle s .
No ch a nge, no effect on oper a tion
1
Intern a l re s et s ign a l gener a tion b it
S PL
0
Ret a ined
High imped a nce 1
Pin s t a te s etting b it
b it15
W W R/W W R/W R/W R/W
b it7 b it6 b it5 b it4 b it 3 b it2 b it1
b it0
R/W
Initi a l v a l u e
S LP
0
No ch a nge, no effect on oper a tion
S witche s to s leep mode.
1
S leep mode b it
S TP
0
No ch a nge, no effect on oper a tion
S witche s to s top mode. 1
S top mode b it
(for time- bas e timer mode a nd s top mode)
:
Re a d ab le a nd writ ab le
: Write only
: Initi a l v a l u e
W
R/W
0