Fujitsu MB90390 Series, Hardware Manual

Page: 319 / 740

291
CHAPTER 18 8/10-BIT A/D CONVERTER
Table 18.4-2 Function Description of Each Bit of Control Status Register 0 (ADCS0)
Bit name Function
bit7
bit6
MD1, MD0:
A/D conversion
mode select bit
• These bits select the conversion mode of the A/D conversion function.
• The two-bit value of the MD1 and MD0 bits determines the mode that is selected from
among four modes: single conversion mode 1, single conversion mode 2, continuous
conversion mode, and stop conversion mode.
• The operation in each mode is described below:
- Single conversion mode 1:
Just a single A/D conversion from the channel set by ANS2 to ANS0 to the channel
set by ANE2 to ANE0 is performed.
Reactivation during operation is allowed.
- Single conversion mode 2:
Just a single A/D conversion from the channel set by ANS2 to ANS0 to the channel
set by ANE2 to ANE0 is performed.
Reactivation during operation is not allowed.
- Continuous conversion mode:
A/D conversion from the channel set by ANS2 to ANS0 to the channel set by ANE2
to ANE0 is performed repeatedly. The repeated conversion continues until it is
stopped by the BUSY bit. Reactivation during operation is not allowed.
- Stop conversion mode:
A/D conversion from the channel set by ANS2 to ANS0 to the channel set by ANE2
to ANE0 is performed repeatedly with a pause after the conversion of each channel.
The repeated conversion continues until it is stopped by the BUSY bit.
Reactivation during operation is not allowed. In the pause state, the conversion is
reactivated when an activation cause selected by the STS1 and STS0 bits is
generated.
Note:
In the single conversion mode, continuous conversion mode, and stop conversion
mode, no reactivation by a timer, external trigger, or software is allowed.
bit5
bit4
bit3
ANS2, ANS1,
ANS0:
A/D conversion
start channel select
bit
• These bits set the A/D conversion start channel and indicate the number of the current
conversion channel.
• When activated, A/D conversion starts from the channel specified by these bits.
• During A/D conversion, the bits indicate the number of the current conversion channel.
During a pause in stop conversion mode, the bits indicate the number of the last
conversion channel.
Note:
Don’t set the bits in this resister using the read-modify-write instruction (RMW) after
the start channels are set for A/D conversion start channel select bits (ANS2, ANS1,
and ANS0).
For ANS2, ANS1, and ANS0 bits, their previous conversion channels are read until A/
D conversion operation starts, therefore, if you set the bits in this resister using the
read-modify-write instruction (RMW) after the start channels are set for ANS2, ANS1,
and ANS0 bits, the values of ANE2, ANE1, and ANE0 bits may be rewritten.
bit2
bit1
bit0
ANE2, ANE1,
ANE0:
A/D conversion
end channel select
bit
• These bits set the A/D conversion end channel.
• When activated, A/D conversion is performed up to the channel specified by these bits.
• When these bits specify the channel specified by ANS2 to ANS0, just that channel is
converted. In continuous or stop conversion mode, the start channel specified by ANS2
to ANS0 is converted after the channel specified by these bits. If the start channel is
greater than the end channel, the start channel to AN7 and AN0 to the end channel are
converted in that order in a single series of conversions.