387
CHAPTER 20 UART2, UART3
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Error detection
If no start/stop bits are selected (ECCR2/ECCR3: SSM = 0) only overrun errors are detected.
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Communication
For initialization of the synchronous mode, following settings have to be done:
Baud rate generator registers (BGR02/BGR03 and BGR12/BGR13):
Set the desired reload value for the dedicated baud rate reload counter.
Serial mode control register (SMR2/SMR3):
MD1, MD0: "10
B
" (Mode 2)
SCKE:
"1" for the dedicated Baud Rate Reload Counter
"0" for external clock input
SOE:
"1" for transmission and reception
"0" for reception only
Serial control register (SCR2/SCR3):
RXE, TXE: set one or both of these flags to "1"
A/D:
no Address/Data selection - don’t care
CL:
automatically fixed to 8-bit data - don’t care
CRE:
"1" to clear error flags and suspend reception.
-- when SSM=0 (default):
PEN, P, SBL: don’t care
-- when SSM=1:
PEN:
"1" if parity bit is added/detected, "0" if not
P:
"1" for even parity, "0" odd parity
SBL:
"1" for 2 stop bits, "0" for 1 stop bit.
Serial status register (SSR2/SSR3):
BDS:
"0" for LSB first, "1" for MSB first
RIE:
"1" if interrupts are used; "0" reception interrupts are disabled.
TIE:
"1" if interrupts are used; "0" transmission interrupts are disabled.
Extended communication control register (ECCR2/ECCR3):
SSM: "0" if no start/stop bits are desired (normal); "1" for adding start/stop bits (extended function)
MS:
"0" for master mode (UART2, UART3 generates the serial clock); "1" for slave mode (UART2,
UART3 receives serial clock from the master device)
Note:
To start the communication, write the data into the transmission data resister (TDR2/TDR3).
If you just want to receive the data, disable the serial output (SMR2/SMR3: SOE = 0) and write a
dummy data to TDR2/TDR3.
Allowing the continuous clock and start/stop bits will enable a bidirectional communication like the
asynchronous mode.
Summary of Contents for MB90390 Series
Page 2: ......
Page 4: ......
Page 17: ...xiii APPENDIX D List of Interrupt Vectors 690 INDEX 695 ...
Page 18: ...xiv ...
Page 132: ...104 CHAPTER 5 CLOCKS ...
Page 152: ...124 CHAPTER 6 CLOCK MODULATOR ...
Page 210: ...182 CHAPTER 11 TIME BASE TIMER ...
Page 218: ...190 CHAPTER 12 WATCHDOG TIMER ...
Page 264: ...236 CHAPTER 14 16 BIT RELOAD TIMER WITH EVENT COUNT FUNCTION ...
Page 274: ...246 CHAPTER 15 WATCH TIMER ...
Page 306: ...278 CHAPTER 17 DTP EXTERNAL INTERRUPTS ...
Page 338: ...310 CHAPTER 18 8 10 BIT A D CONVERTER ...
Page 364: ...336 CHAPTER 19 UART0 UART1 ...
Page 398: ...370 CHAPTER 20 UART2 UART3 Figure 20 5 2 ORE Set Timing Receive data RDRF ORE ...
Page 432: ...404 CHAPTER 20 UART2 UART3 ...
Page 482: ...454 CHAPTER 22 SERIAL I O ...
Page 560: ...532 CHAPTER 24 STEPPING MOTOR CONTROLLER ...
Page 582: ...554 CHAPTER 27 ROM MIRRORING MODULE ...
Page 632: ...604 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION ...
Page 722: ...694 APPENDIX ...
Page 723: ...695 INDEX The index follows on the next page This is listed in alphabetic order ...
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