Fujitsu MB90390 Series, Hardware Manual

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CHAPTER 13 16-BIT I/O TIMER
13.3.2 Control Status Register
The control status register sets the operation mode of the 16-bit free-run timer, starts
and stops the 16-bit free-run timer, and controls interrupts.
■
Control Status Register of Free-run Timer (Lower)
Figure 13.3-3 Control Status Register of Free-run Timer (TCCSL0/TCCSL1)
7 6 5 4 3 2 1 0
R/W
bit 2 bit1 bit 0
CLK2 CLK1 CLK0 Count Clock Selection
0 0 0
φ
0 0 1
φ
/ 2
0 1 0
φ
/ 4
0 1 1
φ
/ 8
1 0 0
φ
/ 16
1 0 1
φ
/ 32
1 1 0
φ
/ 64
1 1 1
φ
/ 128
φ
= MCU clock
bit 3
CLR
Clear Timer
Read Write
0
read al w ays "0"
no effect
1 clear timer to "0000
B
"
bit 4
MODE
0 Initialization by reset or clear bit
1 Init. by reset, clear bit, or compare reg. 0 (4)
bit 5
STOP
0 Counter enabled
1 Counter disabled (stop)
bit 6
IVFE Interrupt enable bit
0 Interrupt disabled
1 Interrupt enabled
bit 7
IVF
Interrupt request flag bit
Read Write
0 No interrupt clear this bit
1 Interrupt request no effect
R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0
Initial value
R/W : Readable and w ritable
: Initial value
B
00352E
00353E
H
H
TCCSL0/TCCSL1
bit Address:
Set Reset condition of timer
Stop the timer
CLK2 CLK1 CLK0
CLR MODE STOP
IVFE
IVF