Fujitsu MB90390 Series, Hardware Manual, Page: 661 / 740

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APPENDIX B Instructions
●
Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
●
Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction a 4 + disp16). The offset is one
word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the
operand address of each of the following instructions is not deemed to be (next instruction a
disp16):
• DBNZ eam, rel
• DWBNZ eam, rel
• CBNE eam, #imm8, rel
• CWBNE eam, #imm16, rel
• MOV eam, #imm8
• MOVW eam, #imm16
Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with
an offset and stores it in A.)
Before execution A 0 7 1 6 2 5 3 4
(+25
H
) Memory space
RL2 F 3 8 2 4 B 0 2 824B27
H
E E
824B28
H
F F
After execution A 2 5 3 4 F F E E
RL2 F 3 8 2 4 B 0 2
MOVW A, @PC+20H (This instruction reads data by program counter indirect
addressing with an offset and stores it in A.)
Before execution A 0 7 1 6 2 5 3 4 Memory space
PCB C 5 PC 4 5 5 6 C54556
H
7 3
MOVW
A, @PC+20
H
C54557
H
9 E
C54558
H
2 0
C54559
H
0 0
After execution A 2 5 3 4 F F E E
+4
C5455A
H
.
.
.
PCB C 5 PC 4 5 5 A
+20
H
C5457A
H
E E
C5457B
H
F F