Fujitsu MB90390 Series, Hardware Manual

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CHAPTER 15 WATCH TIMER
15.2 Watch Timer Registers
The Watch Timer has the following five types of registers:
• Timer control register (WTCR)
• Subsecond register (WTBR)
• Second register (WTSR)
• Minute register (WTMR)
• Hour register (WTHR)
■
Watch Timer Registers
Figure 15.2-1 Watch Timer Registers
Notes:
• Clearing the clock counter affects the watchdog counter and interval interrupts that use clock
timer output.
• To clear the clock timer by writing "0" to the WTR bit in the clock timer control register (WTCR),
set the WTIE bit to "0" and set the clock timer to interrupt inhibited state. Before permitting an
interrupt, clear the interrupt request issued by writing "0" to the WTOF flag.
Timer control regi s ter
Addre ss :
000060
000061
H
H
WTCR
15 14 1 3 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W R/W R/W - - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 X X 0 0 0 0 0 0 0 0 0 0 0
Initi a l v a l u e:
Re s erved Re s erved Re s erved UPDT OE S T INTE 3 INT 3 INTE2 INT2 INTE1 INT1 INTE0 INT0
Sub - s econd regi s ter (0)
Addre ss :
00 3 54A
00 3 54B
H
H
WTBR0
15 14 1 3 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
X X X X X X X X X X X X X X X X Initi a l v a l u e:
D10 D9 D 8 D7 D6 D5 D4 D 3 D2 D1 D0 D15 D14 D1 3 D12 D11
S econd regi s ter/
Addre ss :
00 3 54C
00 3 54D
H
H
WTBR1
15 14 1 3 12 11 10 9 8 7 6 5 4 3 2 1 0
- - R/W R/W R/W R/W R/W R/W - - R/W R/W R/W R/W R/W R/W
X X X X X X X X X X X X X X X X Initi a l v a l u e:
S 2 S 1
S 0
- - D21 D20 D19 D1 8 D17 D16 - - S 5 S 4 S3
- -
Ho u r Regi s ter/
Addre ss :
00 3 54E
00 3 54F
H
H
WTMR
15 14 1 3 12 11 10 9 8 7 6 5 4 3 2 1 0
- - - R/W R/W R/W R/W R/W - - R/W R/W R/W R/W R/W R/W
X X X X X X X X X X X X X X X X Initi a l v a l u e:
H2 H1 H0 - - M5 M4 M 3 M2 M1 M0 - - - H4 H 3
WT S R
Min u te Regi s ter
WTHR
Sub - s econd regi s ter (1)
b it
b it
b it
b it