Fujitsu MB90390 Series, Hardware Manual, Page: 288 / 740

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CHAPTER 16 8/16-BIT PPG
Table 16.3-3 Bit Function Description of the Clock Select Register (PPG01)
Bit name Function
bit7 to bit5
PCS2 to PCS0:
Count clock selection
bit
These bits select the operation clock for the down counter of Channel 1 as described
below.
Note:
In 8-bit pre 8-bit PPG mode or in 16-bit PPG mode, ch.1 PPG operates in
response to a counter clock from ch.0. Therefore, the setting in these bits has no
effect.
bit4 to bit2
PCM2 to PCM0:
Count clock selection
bit
These bits select the operation clock for the down counter of Channel 0 as described
below.
PC S 2 PC S 1 PC S 0 Operation mode
0 0 0 Peripher a l Clock (62.5 n s m a chine clock, 16 MHz)
0 0 1 Peripher a l Clock/2 (125 n s m a chine clock, 16 MHz)
0 1 0 Peripher a l Clock/4 (250 n s m a chine clock, 16 MHz)
0 1 1 Peripher a l Clock/ 8 (500 n s m a chine clock, 16 MHz)
1 0 0 Peripher a l Clock/16 (1
μ
s m a chine clock, 16 MHz)
1 1 1
Clock inp u t from the time- bas e timer
(12 8
μ
s , 4 MHz s o u rce o s cill a tion)
PCM2 PCM1 PCM0 Operation mode
0 0 0
Peripheral Clock (62.5 ns machine clock, 16 MHz)
0 0 1
Peripheral Clock/2 (125 ns machine clock, 16 MHz)
0 1 0
Peripheral Clock/4 (250 ns machine clock, 16 MHz)
0 1 1
Peripheral Clock/8 (500 ns machine clock, 16 MHz)
1 0 0
Peripheral Clock/16 (1
μ
s machine clock, 16 MHz)
1 1 1
Clock input from the time-base timer
(128
μ
s, 4 MHz source oscillation)