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399
CHAPTER 20 UART2, UART3
20.7.8
Sample Flowcharts for UART2, UART3 in LIN
Communication (Operation Mode 3)
This section contains sample flowcharts for UART2, UART3 in LIN communication.
■
UART2, UART3 as Master Device
Figure 20.7-18 UART2, UART3 LIN Master Flow Chart
S
TART
S
end Me
ssa
ge?
YE
S
Initi
a
l
s
etting :
S
et oper
a
tion mode
3
S
eri
a
l d
a
t
a
o
u
tp
u
t en
ab
led
B
au
d r
a
te
s
etting
S
ynch
b
re
a
k length
s
etting
TXE=1, TIE=0
RXE=1, RIE=1
S
ynch
b
re
a
k interr
u
pt
Reception en
ab
led
LBD=0
S
ynch
b
re
a
k interr
u
pt di
sab
led
LBD=1
S
ynch field reception
Identify field
s
et : TDR2/TDR
3
=ID
*1: Perform
a
n error proce
ss
ing when
a
n error h
as
occ
u
rred.
*2:
•
If FRE
a
nd ORE
b
it
s
a
re "1", write "1" to the CRE
b
it in the
S
CR to cle
a
r the error fl
a
g.
•
If LBD
b
it in the E
S
CR i
s
"1", exec
u
te UART re
s
et.
Note: Perform the error detection in e
a
ch proce
ss
a
nd give proper c
a
re.
*1
*1
ID field reception
*1
D
a
t
a
1 reception
*1
D
a
t
a
N reception
NO
NO
YE
S
YE
S
(reception)
NO (tr
a
n
s
mi
ss
ion)
YE
S
NO
W
a
ke
u
p?
(
8
0
H
reception)
RXE=0
S
ynch
b
re
a
k interr
u
pt en
ab
led
S
ynch
b
re
a
k tr
a
n
s
mi
ss
ion :
ECCR2/ECCR
3
: LBR=1
S
ynch field tr
a
n
s
mi
ss
ion :
TDR2/TDR
3
=55
H
Reception interr
u
pt
RDRF=1
Reception interr
u
pt
RDRF=1
*1
*1
Reception interr
u
pt
RDRF=1
Reception interr
u
pt
RDRF=1
Tr
a
n
s
mi
ss
ion d
a
t
a
1
s
et :
TDR2/TDR
3
=D
a
t
a
1
Tr
a
n
s
mi
ss
ion interr
u
pt
en
ab
led
Tr
a
n
s
mi
ss
ion d
a
t
a
N
s
et :
TDR2/TDR
3
=D
a
t
a
N
Tr
a
n
s
mi
ss
ion interr
u
pt
di
sab
led
Tr
a
n
s
mi
ss
ion interr
u
pt
TDRE=1
Reception interr
u
pt
RDRF=1
Reception interr
u
pt
RDRF=1
D
a
t
a
1 reception
D
a
t
a
1 re
a
ding
D
a
t
a
N reception
D
a
t
a
N re
a
ding
Witho
u
t error
Error proce
ss
ing
*2
D
a
t
a
field reception?
Summary of Contents for MB90390 Series
Page 2: ......
Page 4: ......
Page 17: ...xiii APPENDIX D List of Interrupt Vectors 690 INDEX 695 ...
Page 18: ...xiv ...
Page 132: ...104 CHAPTER 5 CLOCKS ...
Page 152: ...124 CHAPTER 6 CLOCK MODULATOR ...
Page 210: ...182 CHAPTER 11 TIME BASE TIMER ...
Page 218: ...190 CHAPTER 12 WATCHDOG TIMER ...
Page 264: ...236 CHAPTER 14 16 BIT RELOAD TIMER WITH EVENT COUNT FUNCTION ...
Page 274: ...246 CHAPTER 15 WATCH TIMER ...
Page 306: ...278 CHAPTER 17 DTP EXTERNAL INTERRUPTS ...
Page 338: ...310 CHAPTER 18 8 10 BIT A D CONVERTER ...
Page 364: ...336 CHAPTER 19 UART0 UART1 ...
Page 398: ...370 CHAPTER 20 UART2 UART3 Figure 20 5 2 ORE Set Timing Receive data RDRF ORE ...
Page 432: ...404 CHAPTER 20 UART2 UART3 ...
Page 482: ...454 CHAPTER 22 SERIAL I O ...
Page 560: ...532 CHAPTER 24 STEPPING MOTOR CONTROLLER ...
Page 582: ...554 CHAPTER 27 ROM MIRRORING MODULE ...
Page 632: ...604 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION ...
Page 722: ...694 APPENDIX ...
Page 723: ...695 INDEX The index follows on the next page This is listed in alphabetic order ...
Page 740: ......