Fujitsu MB90390 Series, Hardware Manual, Page: 188 / 740

160
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
Note:
If the CPU does not branch to the interrupt processing routine immediately after a return, action such
as interrupt disabling must be taken before a standby mode is set.
■
Release of the Stop Mode
The stop mode can be released by an input that has been set as an external interrupt input cause before the
system enters the stop mode. As an input cause, an "H" signal, "L" signal, rising edge, or falling edge can
be selected.
■
Oscillation Stabilization Wait Time
●
Clock oscillation stabilization wait time
Because the oscillator for oscillation is halted in the stop mode, an oscillation stabilization wait time is
required. A time period selected by the WS1 and WS0 bits of the clock selection register (CKSCR) is used
as the oscillation stabilization wait time. The WS1 and WS0 bits can be set to "00
B
" only in the main clock
mode.
●
PLL clock oscillation stabilization wait time
In main clock mode, the PLL multiplication circuit stops. When changing to PLL clock mode, it is
necessary to reserve the PLL clock oscillation stabilization wait time.
In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop
mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock oscillation
stabilization wait time. The oscillation stabilization wait times for the main clock and PLL clock are
counted simultaneously according to the value specified in the oscillation stabilization wait time selection
bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection
bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the
longer of main clock and PLL clock oscillation stabilization wait time. The PLL clock oscillation
stabilization wait time, however, requires 2
14
/HCLK or more. Set the oscillation stabilization wait time
selection bits (CKSCR: WS1, WS0) in the clock selection register to "10
B
" or "11
B
".
■
Clock Mode Switching
When the clock mode is switched, the mode should not switch to the low power consumption mode, or
other clock mode until the switching termination. To check the switching termination, the MCM bit of the
clock selection register (CKSCR) is read. The other switching to other clock mode or to low power
consumption mode may not be done before the switching termination.