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CHAPTER 20 UART2, UART3
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Transmission operation
If the Transmission Data Register Empty (TDRE) flag bit of the Serial Status Register (SSR2/SSR3) is "1",
transmission data is allowed to be written to the Transmission Data Register (TDR2/TDR3). When data is
written, the TDRE flag goes "0". If the transmission operation is enabled by the TXE-Bit ("1") of the Serial
Control Register (SCR2/SCR3), the data is written next to the transmission shift register and the
transmission starts at the next clock cycle of the serial clock, beginning with the start bit. Thereby the
TDRE flag goes "1", so that new data can be written to the TDR2/TDR3.
If transmission interrupt is enabled (TIE = 1), the interrupt is generated by the TDRE flag. Note, that the
initial value of the TDRE flag is "1", so that in this case if TIE is set to "1" an interrupt will occur
immediately.
When the data length is set to 7 bits (CL=0), the unused bit of the TDR2/TDR3 is always the MSB,
independently from the transfer direction setting in the BDS bit (LSB first or MSB first).
Note:
Because the initial value of the transmission data empty flag bit (SSR2/SSR3:TDRE) is "1",
if the transmission interrupt is enabled (SSR2/SSR3:TIE=1), an interrupt generates immediately.
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Reception operation
Reception operation is performed when it is enabled by the Reception Enable (RXE) flag bit of the SCR2/
SCR3. If a start bit is detected, a data frame is received according to the format specified by the SCR2/
SCR3. In case of errors, the corresponding error flags are set (PE, ORE, FRE). After the reception of the
data frame the data is transferred from the reception shift register to the Reception Data Register (RDR2/
RDR3) and the Receive Data Register Full (RDRF) flag bit of the SSR2/SSR3 is set to "1". The data then
has to be read by the CPU. By doing so, the RDRF flag is cleared. If reception interrupt is enabled (RIE =
1), the interrupt is simply generated by the RDRF. To read received data, check the error flag status upon
completion of reception of one-frame data and, if the data has been received normally, read the received
data from the Reception Data Register (RDR2/RDR3). If a reception error has occurred, perform error
handling.
When the data length is set to 7 bits (CL=0), the unused bit of the RDR2/RDR3 is always the MSB,
independently from the transfer direction setting in the BDS bit (LSB first or MSB first).
Note:
Only when the RDRF flag bit is set and no errors have occurred the Reception Data Register (RDR2/
RDR3) contains valid data.
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Used clock
Use the internal clock or external clock. Select the baud rate generator (SMR2/SMR3: EXT = 0 or 1, OTO =
0) for desired baud rate.
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Stop bit
One or two stop bits can be selected at transmission. If two stop bits are selected, both of the stop bits are
detected at reception. Upon detection of the first stop bit, the reception data register full flag (SSR2/
SSR3:RDRF) is set to "1". If no start bit is detected subsequently, the reception bus idle flag (ECCR2/
ECCR3:RBI) is set to "1" to indicate no reception.
Summary of Contents for MB90390 Series
Page 2: ......
Page 4: ......
Page 17: ...xiii APPENDIX D List of Interrupt Vectors 690 INDEX 695 ...
Page 18: ...xiv ...
Page 132: ...104 CHAPTER 5 CLOCKS ...
Page 152: ...124 CHAPTER 6 CLOCK MODULATOR ...
Page 210: ...182 CHAPTER 11 TIME BASE TIMER ...
Page 218: ...190 CHAPTER 12 WATCHDOG TIMER ...
Page 264: ...236 CHAPTER 14 16 BIT RELOAD TIMER WITH EVENT COUNT FUNCTION ...
Page 274: ...246 CHAPTER 15 WATCH TIMER ...
Page 306: ...278 CHAPTER 17 DTP EXTERNAL INTERRUPTS ...
Page 338: ...310 CHAPTER 18 8 10 BIT A D CONVERTER ...
Page 364: ...336 CHAPTER 19 UART0 UART1 ...
Page 398: ...370 CHAPTER 20 UART2 UART3 Figure 20 5 2 ORE Set Timing Receive data RDRF ORE ...
Page 432: ...404 CHAPTER 20 UART2 UART3 ...
Page 482: ...454 CHAPTER 22 SERIAL I O ...
Page 560: ...532 CHAPTER 24 STEPPING MOTOR CONTROLLER ...
Page 582: ...554 CHAPTER 27 ROM MIRRORING MODULE ...
Page 632: ...604 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION ...
Page 722: ...694 APPENDIX ...
Page 723: ...695 INDEX The index follows on the next page This is listed in alphabetic order ...
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