Fujitsu MB90390 Series, Hardware Manual

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94
CHAPTER 5 CLOCKS
bit10
MCS:
Machine clock
selection bit
• This bit specifies whether the main clock or a PLL clock is selected as the machine
clock.
• When this bit is "0", a PLL clock is selected. When it is 1, the main clock is selected.
• If this bit has been set to "1" and "0" is written to it, the oscillation stabilization wait
time for the PLL clock starts. As a result, the time-base timer is automatically cleared,
and the TBOF bit of the time-base timer control register (TBTC) is also cleared.
• For PLL clocks, the oscillation stabilization wait time is fixed at 2
14
/HCLK (the
oscillation stabilization wait time is approx. 4.1 ms for an oscillation clock frequency of
4 MHz).
• When the main clock has been selected, the operating clock frequency is the oscillation
clock frequency divided by 2 (that is, the operating clock is 2 MHz when the oscillation
clock frequency is 4 MHz).
• This bit is initialized to "1" by all reset causes.
Note:
When the MCS bit is "1", write "0" to it only when the time-base timer interrupt is
masked by the TBIE bit of the time-base timer control register (TBTC) or the interrupt
level register (ILM).
bit9
bit8
CS1 and CS0:
Multiplier selection
bits
• These bits and CS2 bit in PSCCR register select a PLL clock multiplier.
• Selection can be made from among six different multipliers.
• These bits are initialized to "00
B
"by all reset causes.
• Recommended settings of CS2 to CS0:
Note:
When the MCS or MCM bit is "0", writing to these bits is not allowed. Write to the
CS2, CS1 and CS0 bits only after setting the MCS bit to "1" (main clock mode).
HCLK: Oscillation clock
Table 5.3-1 Clock Selection Register (CKSCR) (2/2)
Bit name Function
C S 1 C S 0 PLL clock multiplier
0 0
0 1
1 0
1 1
C S 2
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
× 1 For m a chine clock u p to 20MHz *
1
× 2 For m a chine clock u p to 20MHz *
1
× 3 For m a chine clock u p to 20MHz *
1
× 4 For m a chine clock u p to 20MHz *
1
× 2 For m a chine clock ab ove 20MHz *
1
× 4 For m a chine clock ab ove 20MHz *
1
× 6 For m a chine clock ab ove 20MHz *
1
× 8 *
2
For m a chine clock ab ove 20MHz *
1
*1 : Refer to the AC Ch a r a cteri s tic s S ection in the D a t a S heet.
*2 : Not s pecified for a ll device s . Refer to the AC Ch a r a cteri s tic s S ection in the D a t a S heet.