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CHAPTER 28 3M-BIT FLASH MEMORY
28.4
Flash Memory Control Status Register (FMCS)
The flash memory control status register (FMCS), together with the flash memory
interface circuit, is used to write data to and erase data from the flash memory.
■
Flash Memory Control Status Register (FMCS)
Figure 28.4-1 Flash Memory Control Status Register (FMCS)
●
Explanation of bits
[bit7] INTE (interrupt enable)
This bit generates an interrupt to the CPU when flash memory write/erase terminates.
An interrupt to the CPU is generated when the INTE and RDYINT bits are "1". No interrupt is
generated when the INTE bit is "0".
•
"0": Disables interrupts when write/erase terminates.
•
"1": Enables interrupts when write/erase terminates.
[bit6] RDYINT (ready interrupt)
This bit indicates the operating state of the flash memory.
This bit is set to "1" when flash memory write/erase terminates. Data cannot be written to or erased
from the flash memory while this bit is "0" after a flash memory write/erase. Flash memory write/erase
is enabled when write/erase terminates and this bit is set to "1".
Writing "0" clears this bit to "0". Writing "1" is ignored. This bit is set to "1" at the termination timing
of the flash memory automatic algorithm (see Section "28.5 Starting the Flash Memory Automatic
Algorithm"). When the read-modify-write (RMW) instruction is used, "1" is always read.
•
"0": Write/erase is being executed.
•
"1": Write/erase has terminated (interrupt request generated).
[bit5] WE (write enable)
This bit enables writing to the flash memory area.
When this bit is "1", writing after the command sequence (see Section "28.5 Starting the Flash Memory
Automatic Algorithm") is issued to the F8 (F9) to FF bank writes to the flash memory area. When this
bit is "0", the write/erase signal is not generated. This bit is used when the flash memory Write/Erase
command is started.
If write/erase is not performed, it is recommended that this bit be set to "0" to prevent data from being
mistakenly written to the flash memory.
•
"0": Disables flash memory write/erase.
•
"1": Enables flash memory write/erase.
7
6
5
4
3
2
1
0
INTE
RDYINT
WE
RDY
Reserved
Reserved
Reserved
Reserved
(R/W)
(R/W)
(R/W)
(R)
(R/W)
(R/W)
(R/W)
(R/W)
Address: 0000AE
bit
H
Initial value
000X0000
B
Summary of Contents for MB90390 Series
Page 2: ......
Page 4: ......
Page 17: ...xiii APPENDIX D List of Interrupt Vectors 690 INDEX 695 ...
Page 18: ...xiv ...
Page 132: ...104 CHAPTER 5 CLOCKS ...
Page 152: ...124 CHAPTER 6 CLOCK MODULATOR ...
Page 210: ...182 CHAPTER 11 TIME BASE TIMER ...
Page 218: ...190 CHAPTER 12 WATCHDOG TIMER ...
Page 264: ...236 CHAPTER 14 16 BIT RELOAD TIMER WITH EVENT COUNT FUNCTION ...
Page 274: ...246 CHAPTER 15 WATCH TIMER ...
Page 306: ...278 CHAPTER 17 DTP EXTERNAL INTERRUPTS ...
Page 338: ...310 CHAPTER 18 8 10 BIT A D CONVERTER ...
Page 364: ...336 CHAPTER 19 UART0 UART1 ...
Page 398: ...370 CHAPTER 20 UART2 UART3 Figure 20 5 2 ORE Set Timing Receive data RDRF ORE ...
Page 432: ...404 CHAPTER 20 UART2 UART3 ...
Page 482: ...454 CHAPTER 22 SERIAL I O ...
Page 560: ...532 CHAPTER 24 STEPPING MOTOR CONTROLLER ...
Page 582: ...554 CHAPTER 27 ROM MIRRORING MODULE ...
Page 632: ...604 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION ...
Page 722: ...694 APPENDIX ...
Page 723: ...695 INDEX The index follows on the next page This is listed in alphabetic order ...
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