Fujitsu MB90390 Series, Hardware Manual

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CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.2.1 Timer Control Status Register (TMCSR)
Controls the operation mode and interrupts for the 16-bit timer. Only modify bits other
than UF, CNTE, and TRG when CNTE = 0.
■
Register Layout of Timer Control Register (TMCSR)
■
Register Contents of Timer Control Register (TMCSR)
[bit11, bit10] CSL1, CSL0 (Clock select 1, 0)
The count clock select bits. Table 14.2-1 lists the clock sources for CSL bit settings.
15 bit
bit
14 13 12 11 10 9 8
X X X X 0 0 0 0
Initial value
B
Address:
000051
000053
H
H
TMCSR0/TMCSR1 (upper)
CSL1 CSL0 MOD2 MOD1
- - - -
- - - - R/W R/W R/W R/W
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
Initial value
B
Address:
000050
000052
H
H
TMCSR0/TMCSR1 (lo w er)
MOD0 OUTE OUTL RELD I NTE UF CNTE TRG
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable and w ritable
X : Undefined value
- : Undefined
Table 14.2-1 Clock Sources for CSL Bit Settings
CSL1 CSL0 Clock Source (Machine cycle
φ
= 16 MHz)
0 0
φ
/2
1
(0.125
μ
s)
0 1
φ
/2
3
(0.5
μ
s)
1 0
φ
/2
5
(2.0
μ
s)
1 1 External event count mode