Fujitsu MB90390 Series, Hardware Manual

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CHAPTER 17 DTP/EXTERNAL INTERRUPTS
17.5 Notes on Using DTP/External Interrupts
Note carefully the following items when using DTP/external interrupts:
• Conditions on the externally connected peripheral when DTP is used
• External interrupt/DTP operation procedure
• External interrupt request level
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Notes on Using DTP/External Interrupts
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Conditions on the externally connected peripheral when DTP is used
DTP supports only external peripherals that automatically clear a request once a transfer is completed. The
system must be designed so that a transfer request is canceled within three machine cycles (provisional)
after transfer operation starts. Otherwise, this resource assumes that a transfer request is issued.
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External interrupt/DTP operation procedure
To set registers in the external interrupt/DTP, follow the steps below:
1. Set the general-purpose I/O pin shared with the pin for using the external interrupt input as the input port.
2. Disable the bits corresponding to the enable register.
3. Set the bits corresponding to the request level setting register.
4. Clear the bits corresponding to the cause register.
5. Enable the bits corresponding to the enable register.
(Steps 4. and 5. can be simultaneously performed by word specification.)
To set a register in this resource, ensure that the enable register is disabled. Before enabling the enable
register, ensure that the cause register is cleared. Clearing the cause register prevents a false interrupt cause
from being determined while registers are set or interrupts are enabled.
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External interrupt request level
To detect an edge for an edge request you need at least the minimum pulse width described in datasheet.
Please refer to it.
As shown in Figure 17.5-1, when the request input level is related to the level setting, a request that is input
from an external device to the interrupt controller is kept active even if the request is later canceled because
a cause hold circuit has been installed. To cancel the request to the interrupt controller, the cause hold
circuit must be cleared as shown in Figure 17.5-2.
Figure 17.5-1 Clearing the Cause Hold Circuit Upon Level Set
Interrupt cause
Cause F/F (interrupt/DTP
cause register)
The cause is kept held unless cleared.
Enable gate
To interrupt
controller
Level detection