Fujitsu MB90390 Series, Hardware Manual, Page: 447 / 740

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CHAPTER 21 400 kHz I
2
C INTERFACE
• Note on using the devices except MB90F394H(A) and MB90V390H.
If the device is used in the following condition, it cannot receive as slave. So, sending general call
address is prohibited.
- Condition that there is other master mode LSI on the bus without MB90390 series, and
MB90390 series transmit the general-call address as master, and the arbitration lost occurs
after second byte.
• When an instruction which generates a start condition is executed (the MSS bit is set to "1") at the
timing shown in Figure 21.2-3 and Figure 21.2-4, arbitration lost detection (AL bit = 1) prevents an
interrupt (INT bit = 1) from being generated.
- Condition 1 in which an interrupt (INT bit = 1) upon detection of " AL bit = 1 " does not occurs
When an instruction which generates a start condition is executed (setting the MSS bit in the
IBCR register to 1) with no start condition detected (BB bit = 0) and with the SDA or SCL pin at
the " L " level.
Figure 21.2-3 Diagram of Timing at which an Interrupt Upon Detection of " AL Bit = 1 " does not Occurs
"L"
"L"
1
0
0
SCL pin or SDA pin is Low level.
SCL pin
SDA pin
I
2
C operation enable state (EN bit =1)
Master mode setting (MSS bit = 1)
Arbitration lost detection (AL bit = 1)
Bus busy (BB bit)
Interruption (INT bit)