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CHAPTER 18 8/10-BIT A/D CONVERTER
●
Coding example
BAPL EQU 000100H ;Lower buffer address pointer
BAPM EQU 000101H ;Intermediate buffer address pointer
BAPH EQU 000102H ;Upper buffer address pointer
ISCS EQU 000103H ;EI
2
OS status register
IOAL EQU 000104H ;Lower I/O address register
IOAH EQU 000105H ;Upper I/O address register
DCTL EQU 000106H ;Lower data counter
DCTH EQU 000107H ;Upper data counter
DDR6 EQU 000016H ;Port 6 direction register
ADER0 EQU 00000CH ;Analog input enable register
ICR10 EQU 0000BAH ;Interrupt control register for A/D Converter
ADCS0 EQU 000034H ;A/D control status register
ADCS1 EQU 000035H ;
ADCR0 EQU 000036H ;A/D data register
ADCR1 EQU 000037H ;
;-----Main program---------------------------------------------------------------
CODE CSEG
START: ;Assumes that the stack pointer (SP) has already
;been initialized.
AND CCR,#0BFH ;Disables interrupts.
MOV ICR10,#00H ;Interrupt level: 0 (highest priority)
MOV BAPL,#00H ;Sets the address to which the conversion data is
;transferred and stored.
MOV BAPM,#02H ;(Uses 200
H
to 205
H
.)
MOV BAPH,#00H ;
MOV ISCS,#18H ;Transfers word data, adds 1 to the address,
; then transfers the data from I/O to memory.
MOV IOAL,#36H ;Sets the address of the analog data register as
MOV IOAH,#00H ;the transfer source address pointer.
MOV DCTL,#03H ;Sets the EI
2
OS transfer count to three, which is
;the same value as the conversion count.
MOV DDR6,#11110001B ;Sets P61 to P63 as input.
MOV ADER0,#00001110B ;Sets P61/AN1 to P63/AN3 as analog inputs.
MOV CTH,#00H ;
MOV ADCS0,#0BH ;Single activation. Converts AN1 to AN3.
MOV ADCS1,#0A2H ;Software activation. Begins A/D conversion.
;Enables interrupts.
MOV ILM,#07H ;Sets ILM in PS to level 7.
OR CCR,#40H ;Enables interrupts.
LOOP:
MOV A,#00H ;Endless loop
MOV A,#01H
BRA LOOP
Summary of Contents for MB90390 Series
Page 2: ......
Page 4: ......
Page 17: ...xiii APPENDIX D List of Interrupt Vectors 690 INDEX 695 ...
Page 18: ...xiv ...
Page 132: ...104 CHAPTER 5 CLOCKS ...
Page 152: ...124 CHAPTER 6 CLOCK MODULATOR ...
Page 210: ...182 CHAPTER 11 TIME BASE TIMER ...
Page 218: ...190 CHAPTER 12 WATCHDOG TIMER ...
Page 264: ...236 CHAPTER 14 16 BIT RELOAD TIMER WITH EVENT COUNT FUNCTION ...
Page 274: ...246 CHAPTER 15 WATCH TIMER ...
Page 306: ...278 CHAPTER 17 DTP EXTERNAL INTERRUPTS ...
Page 338: ...310 CHAPTER 18 8 10 BIT A D CONVERTER ...
Page 364: ...336 CHAPTER 19 UART0 UART1 ...
Page 398: ...370 CHAPTER 20 UART2 UART3 Figure 20 5 2 ORE Set Timing Receive data RDRF ORE ...
Page 432: ...404 CHAPTER 20 UART2 UART3 ...
Page 482: ...454 CHAPTER 22 SERIAL I O ...
Page 560: ...532 CHAPTER 24 STEPPING MOTOR CONTROLLER ...
Page 582: ...554 CHAPTER 27 ROM MIRRORING MODULE ...
Page 632: ...604 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION ...
Page 722: ...694 APPENDIX ...
Page 723: ...695 INDEX The index follows on the next page This is listed in alphabetic order ...
Page 740: ......