Fujitsu MB90390 Series, Hardware Manual

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CHAPTER 6 CLOCK MODULATOR
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Modulation Parameter Register Contents
Table 6.3-3 Function of Each Bit of the Modulation Parameter Register (CMPR)
Bit name Function
bit15,
bit14
Undefined -
bit13 to
bit0
MP13 to MP0:
Modulation
Parameter bits Depending on the PLL frequency the following modulation parameter settings are
possible. The corresponding CMPR register value is stated in the most right column.
F0: Frequency of unmodulated input clock (PLL frequency)
T0: Period of unmodulated input clock (PLL clock period)
resolution: resolution of frequencies in the modulated clock. "L" (1) to "H" (7)
F
min
: minimal frequency occurring in the frequency modulated clock
F
max
: maximal frequency occurring in the frequency modulated clock
phase skew: The maximal phase shift of the modulated clock relative to the unmodulated
reference clock in terms of clock periods of the unmodulated clock.
Example: phase skew=1.44
In worst case, a sequence of n periods of the modulated clock can be 1.44
×
T0
shorter or 1.44
×
T0 longer than a sequence of n periods of the unmodulated
reference clock.
n can be any number > 50 periods
phase skew 50: phase skew for sequences with n<= 50 periods
CMPR: register setting of the CMPR register
n periods
n periods
n periods
reference clock
mod u lated clock
phase skew
+
-