625
SB-RMI
Writes
May
Not
Be
Observed
by
Processor
Description
After
a
write
using
the
APML
SB-RMI
interface
to
either
the
Inbound
Message
Registers
(
SBRMI
_
x
3[
F
:8])
or
Software
Interrupt
Register
(
SBRMI
_
x
40),
the
processor
may
observe
the
previous
contents
(
as
if
the
write
did
not
occur
)
when
reading
these
same
registers
using
the
SBI
Address
/
Data
registers
(
D
18
F
3
x
1
E
8
and
D
18
F
3
x
1
EC
).
The
conditions
under
which
this
erratum
may
occur
requires
that
message-triggered
C
1
E
is
enabled
(
D
18
F
3
xD
4[13] = 1
b
,
Clock
Power
/
Timing
Control
0[
MTC
1
eEn
]).
The
functionality
of
the
SB-RMI
interface
is
not
otherwise
affected
.
Potential
Effect
on
System
Software
running
on
the
processor
is
not
able
to
properly
receive
messages
from
system
management
software
using
the
SB-RMI
interface
.
Suggested
Workaround
None
.
In
the
event
that
system
management
software
needs
to
communicate
with
software
running
on
the
processor
,
an
alternative
mechanism
should
be
used
.
Fix
Planned
No
fix
planned
48063
Rev
. 3.18
October
2012
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
Product
Errata
45