668
Load
Operation
May
Receive
Incorrect
Data
After
Floating-
point
Exception
Description
The
processor
may
incorrectly
load
data
from
a
prior
store-to-load
forwarding
operation
after
an
unmasked
x
87
floating-point
exception
(#
MF
)
if
the
exception
occurs
while
CR
0
Numeric
Error
= 0
b
(
CR
0.
NE
,
bit
5)
and
a
prior
exception
is
indicated
(
x
87
Status
Word
Register
Exception
Status
,
FSW
.
ES
bit
7,
is
already
1
b
).
Potential
Effect
on
System
None
expected
.
Operating
systems
typically
set
CR
0.
NE
= 1
b
or
floating-point
exception
handlers
normally
clear
the
exception
status
(
FSW
.
ES
).
If
these
conditions
are
not
met
,
a
load
operation
may
receive
data
that
was
not
updated
by
the
most
current
write
from
a
processor
core
.
AMD
has
not
observed
this
erratum
with
any
commercially
available
software
.
Suggested
Workaround
None
.
Fix
Planned
Yes
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
48063
Rev
. 3.18
October
2012
56
Product
Errata