726
Processor
May
Report
Incorrect
MCA
Address
for
Loads
that
Cross
Address
Boundaries
Description
In
the
event
that
a
line
fill
error
or
system
read
data
error
is
reported
for
some
,
but
not
all
,
bytes
of
an
unaligned
load
instruction
that
crosses
a
cache
line
boundary
(64
bytes
),
the
processor
may
intermittently
report
the
address
of
the
unaffected
cache
line
in
MC
0_
ADDR
(
MSR
0000_0402).
Potential
Effect
on
System
None
expected
.
Suggested
Workaround
None
.
Fix
Planned
No
fix
planned
48063
Rev
. 3.18
October
2012
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
Product
Errata
81