657
MC
1_
STATUS
Enable
Bit
Not
Set
When
Logging
Corrected
Errors
Description
The
processor
does
not
set
MC
1_
STATUS
[
En
] = 1
b
(
MSR
0000_0405[60])
when
logging
an
enabled
and
corrected
error
in
the
IF
machine
check
register
bank
(
bank
1).
Software
can
identify
the
corrected
errors
that
are
affected
by
this
erratum
when
it
observes
an
MC
1_
STATUS
register
with
all
of
the
following
:
•
MC
1_
STATUS
[
Valid
] (
bit
63) = 1
b
•
MC
1_
STATUS
[
Uc
] (
bit
61) = 0
b
•
MC
1_
STATUS
[
En
] (
bit
60) = 0
b
•
MC
1_
STATUS
[
Pcc
] (
bit
57) = 0
b
•
The
corresponding
enable
bit
in
MC
1_
CTL
(
MSR
0000_0404) = 1
b
Potential
Effect
on
System
None
expected
.
Suggested
Workaround
None
required
.
Fix
Planned
No
fix
planned
48063
Rev
. 3.18
October
2012
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
Product
Errata
49