Conventions
Numbering
•
Binary
numbers
.
Binary
numbers
are
indicated
by
appending
a
"b"
at
the
end
,
e
.
g
., 0110
b
.
•
Decimal
numbers
.
Unless
specified
otherwise
,
all
numbers
are
decimal
.
This
rule
does
not
apply
to
the
register
mnemonics
.
•
Hexadecimal
numbers
.
Hexadecimal
numbers
are
indicated
by
appending
an
"h"
to
the
end
,
e
.
g
., 45
F
8
h
.
•
Underscores
in
numbers
.
Underscores
are
used
to
break
up
numbers
to
make
them
more
readable
.
They
do
not
imply
any
operation
.
e
.
g
., 0110_1100
b
.
•
Undefined
digit
.
An
undefined
digit
,
in
any
radix
,
is
notated
as
a
lower
case
"x"
.
Register
References
and
Mnemonics
In
order
to
define
errata
workarounds
it
is
sometimes
necessary
to
reference
processor
registers
.
References
to
registers
in
this
document
use
a
mnemonic
notation
consistent
with
that
defined
in
the
BIOS
and
Kernel
Developer's
Guide
(
BKDG
)
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
,
order
# 42301.
Each
mnemonic
is
a
concatenation
of
the
register-space
indicator
and
the
offset
of
the
register
.
The
mnemonics
for
the
various
register
spaces
are
as
follows
:
•
IOXXX
:
x
86
-defined
input
and
output
address
space
registers
;
XXX
specifies
the
byte
address
of
the
I
/
O
register
in
hex
(
this
may
be
2
or
3
digits
).
This
space
includes
the
I
/
O-Space
Configuration
Address
Register
(
IOCF
8)
and
the
I
/
O-Space
Configuration
Data
Port
(
IOCFC
)
to
access
configuration
registers
.
•
DZFYxXXX
:
PCI-defined
configuration
space
at
bus
0;
Z
specifies
the
PCI
device
address
in
hex
;
XXX
specifies
the
byte
address
of
the
configuration
register
(
this
may
be
2
or
3
digits
)
in
hex
;
Y
specifies
the
function
number
.
For
example
,
D
18
F
3
x
40
specifies
the
register
at
bus
0,
device
18
h
,
function
3,
address
40
h
.
Some
registers
in
D
18
F
2
xXXX
have
a
_
dct
[1:0]
mnemonic
suffix
,
which
indicates
there
is
one
instance
per
DRAM
controller
(
DCT
).
The
DCT
instance
is
selected
by
DCT
Configuration
Select
[
DctCfgSel
]
(
D
18
F
1
x
10
C
[0]).
•
DZFYxXXX
_
xZZZZZ
:
Port
access
through
the
PCI-defined
configuration
space
at
bus
0;
Z
specifies
the
PCI
device
address
in
hex
;
XXX
specifies
the
byte
address
of
the
data
port
configuration
register
(
this
may
be
2
or
3
digits
)
in
hex
;
Y
specifies
the
function
number
;
ZZZZZ
specifies
the
port
address
(
this
may
be
2
to
7
digits
)
in
hex
.
For
example
,
D
18
F
2
x
9
C
_
x
1
C
specifies
the
port
1
Ch
register
accessed
using
the
data
port
register
at
bus
0,
device
18
h
,
function
2,
address
9
Ch
.
Refer
to
the
BIOS
and
Kernel
Developer's
Guide
(
BKDG
)
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
,
order
# 42301
for
access
properties
.
Some
registers
in
D
18
F
2
xXXX
_
xZZZZZ
have
a
_
dct
[1:0]
mnemonic
suffix
,
which
indicates
there
is
one
instance
per
DRAM
controller
(
DCT
).
The
DCT
instance
is
selected
by
DCT
Configuration
Select
[
DctCfgSel
] (
D
18
F
1
x
10
C
[0]).
•
APICXXX
:
APIC
memory-mapped
registers
;
XXX
is
the
byte
address
offset
from
the
base
address
in
hex
(
this
may
be
2
or
3
digits
).
The
base
address
for
this
space
is
specified
by
the
APIC
Base
Address
Register
(
APIC
_
BAR
)
at
MSR
0000_001
B
.
•
CPUID
FnXXXX
_
XXXX
_
RRR
_
xYYY
:
processor
capability
information
returned
by
the
CPUID
instruction
where
the
CPUID
function
is
XXXX
_
XXXX
(
in
hex
)
and
the
ECX
input
is
YYY
(
if
specified
).
When
a
register
is
specified
by
RRR
,
the
reference
is
to
the
data
returned
in
that
register
.
For
example
,
CPUID
Fn
8000_0001_
EAX
refers
to
the
data
in
the
EAX
register
after
executing
CPUID
instruction
function
8000_0001
h
.
•
MSRXXXX
_
XXXX
:
model
specific
registers
;
XXXX
_
XXXX
is
the
MSR
number
in
hex
.
This
space
is
accessed
through
x
86
-defined
RDMSR
and
WRMSR
instructions
.
•
PMCxXXX
[
Y
]:
performance
monitor
events
;
XXX
is
the
hexadecimal
event
counter
number
programmed
into
MSRC
001_020[
A
,8,6,4,2,0][
EventSelect
] (
PERF
_
CTL
[5:0]
bits
7:0).
Y
,
when
specified
,
signifies
the
unit
mask
programmed
into
MSRC
001_020[
A
,8,6,4,2,0][
UnitMask
] (
PERF
_
CTL
[5:0]
bits
15:8).
48063
Rev
. 3.18
October
2012
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
Conventions
7