724
Unintercepted
Halt
Instruction
May
Cause
Protocol
Machine
Check
or
Unpredictable
System
Behavior
Description
An
unintercepted
halt
instruction
executed
in
guest
mode
may
result
in
a
processor
core
being
in
a
cache-flush-
on-halt
state
while
having
VMCB
data
in
the
cache
.
Potential
Effect
on
System
Northbridge
machine
check
exception
(#
MC
)
for
a
link
protocol
error
.
This
machine
check
exception
causes
a
sync
flood
and
system
reset
under
AMD
recommended
BIOS
settings
.
The
machine
check
has
the
following
signature
:
•
The
MC
4_
STAT
register
(
MSR
0000_0411)
is
equal
to
BA
000020_000
B
0
C
0
F
.
Bit
62 (
error
overflow
)
or
bit
59 (
miscellaneous
valid
)
of
MC
4_
STAT
may
or
may
not
be
set
.
•
Bits
5:1
of
the
MC
4_
ADDR
register
(
MSR
0000_0412)
is
equal
to
one
of
10011
b
, 10100
b
, 11000
b
or
11001.
In
addition
,
it
is
possible
for
unpredictable
system
operation
to
occur
without
a
machine
check
exception
.
For
example
,
a
processor
core
may
not
observe
a
write
that
is
performed
by
another
processor
core
.
AMD
has
not
observed
this
effect
in
any
commercially
available
software
.
Suggested
Workaround
Hypervisors
should
intercept
HLT
instructions
by
setting
VMCB
.
Intercept
_
HLT
(
offset
00
Ch
bit
24)
to
1
b
.
Fix
Planned
No
fix
planned
48063
Rev
. 3.18
October
2012
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
Product
Errata
79