718
Instruction-Based
Sampling
May
Be
Inaccurate
Description
The
processor
may
experience
sampling
inaccuracies
when
Instruction-Based
Sampling
(
IBS
)
is
enabled
in
the
following
cases
:
•
The
processor
may
set
IBS
Op
Data
3
Register
[
IbsDcStToLdCan
,
IbsDcStToLdFwd
] (
MSRC
001_1037[12,
11])
incorrectly
for
load
instructions
that
are
tagged
for
IBS
if
there
was
a
recently
executed
store
instruction
whose
store
address
matches
the
load
address
in
bits
11:0.
•
When
performing
an
IBS
execution
sample
,
the
processor
only
sets
,
but
never
clears
,
the
following
bits
:
•
IbsDcL
2
TlbMiss
(
MSR
C
001_1037[3])
•
IbsDcL
2
TlbHit
2
M
(
MSR
C
001_1037[6])
•
IbsDcL
2
TlbHit
1
G
(
MSR
C
001_1037[19])
•
The
processor
incorrectly
updates
IBS
Op
Data
2
Register
[
NbIbsReqCacheHitSt
,
NbIbsReqDstProc
,
NbIbsReqSrc
] (
MSR
C
001_1036[5,4,2:0])
during
an
IBS
fetch
sample
.
If
both
IBS
execution
sampling
(
IBS
Execution
Control
[
IbsOpEn
],
MSRC
001_1033[17] = 1
b
)
and
IBS
fetch
sampling
(
IBS
Fetch
Control
[
IbsFetchEn
],
MSRC
001_1030[48] = 1
b
)
are
enabled
simultaneously
,
valid
execution
sample
data
may
be
overwritten
by
a
fetch
sample
resulting
in
IBS
data
that
is
inconsistent
with
the
accompanying
IBS
execution
sample
data
.
•
The
processor
may
infrequently
report
an
incorrect
instruction
pointer
in
the
IBS
Fetch
Linear
Address
(
MSRC
001_1031).
Potential
Effect
on
System
Inaccuracies
in
performance
monitoring
software
may
be
experienced
.
Suggested
Workaround
The
following
workarounds
can
be
used
for
the
above
issues
:
•
No
workaround
exists
for
IbsDcStToLdCan
and
IbsDcStToLdFwd
.
These
bits
would
not
significantly
over-
indicate
a
store
to
load
forwarding
with
most
code
.
•
Performance
monitoring
software
should
clear
the
IBS
Op
Data
3
Register
(
MSR
C
001_1037[63:0] = 0)
between
each
IBS
sample
.
•
Performance
monitoring
software
should
not
rely
on
MSRC
001_1036
if
both
IBS
execution
sampling
and
IBS
fetch
sampling
are
enabled
simultaneously
.
•
Performance
monitoring
software
should
not
rely
on
MSRC
001_1031.
Fix
Planned
No
fix
planned
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
48063
Rev
. 3.18
October
2012
76
Product
Errata