667
Processor
May
Generate
Incorrect
P-state
Limit
Interrupts
Description
P-state
limit
changes
due
to
SB-RMI
(
SBI
P-state
Limit
[
PstateLimit
],
MSRC
001_0072[10:8]),
software
(
Software
P-state
Limit
Register
[
SwPstateLimit
],
D
18
F
3
x
68[30:28]),
or
hardware
thermal
control
(
entering
HTC-active
state
,
i
.
e
.
PROCHOT
#
assertion
)
may
generate
duplicate
interrupts
when
Hardware
Thermal
Control
Register
bits
[
PslApicLoEn
,
PslApicHiEn
]
are
not
both
zero
(
D
18
F
3
x
64[7:6] != 00
b
).
The
processor
actually
uses
APM
TDP
Control
[
ApmTdpLimitIntEn
] = 1
b
to
enable
the
generation
of
interrupts
for
P-state
limit
changes
due
to
SB-RMI
,
software
,
or
HTC
,
as
well
as
to
generate
interrupts
for
changes
to
TDP
Limit
3
Register
[
ApmTdpLimit
] (
D
18
F
5
xE
8[28:16]).
Potential
Effect
on
System
Operating
systems
monitoring
processor
P-state
capabilities
may
receive
duplicate
notification
of
P-state
limit
changes
due
to
SB-RMI
,
software
,
or
HTC
.
Suggested
Workaround
BIOS
should
leave
Hardware
Thermal
Control
[
PslApicLoEn
,
PslApicHiEn
]
at
their
default
reset
value
(
D
18
F
3
x
64[7:6] = 00
b
)
and
should
set
APM
TDP
Control
[
ApmTdpLimitIntEn
] (
D
18
F
4
x
16
C
[4]) = 1
b
.
This
workaround
requires
software
to
receive
both
P-state
limit
change
interrupts
and
ApmTdpLimit
change
interrupts
.
Fix
Planned
No
fix
planned
48063
Rev
. 3.18
October
2012
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
Product
Errata
55