691
Processors
Using
1
MB
L
3
Subcaches
May
Execute
a
Write-
Back
Invalidate
Operation
Incorrectly
Description
The
processor
may
fail
to
flush
the
full
address
range
of
L
3
cache
when
executing
a
WBINVD
instruction
,
or
INVD
instruction
with
Hardware
Configuration
Register
[
INVDWBINVD
] = 1
b
(
MSRC
001_0015[4]).
This
occurs
when
the
L
3
cache
is
less
than
8
MB
per
northbridge
and
is
configured
using
at
least
one
1
MB
L
3
subcache
,
as
indicated
by
the
L
3
SubcacheSize
fields
(
L
3
Cache
Parameter
Register
[
L
3
SubcacheSize
[3:0]],
D
18
F
3
x
1
C
4[[15:12],[11:8],[7:4],[3:0]] =
Dh
or
Eh
).
Potential
Effect
on
System
Unpredictable
system
behavior
.
This
has
only
been
observed
by
AMD
as
a
system
hang
while
using
cache
as
general
storage
during
boot
.
Suggested
Workaround
Contact
your
AMD
representative
for
information
on
a
BIOS
update
.
Fix
Planned
No
fix
planned
48063
Rev
. 3.18
October
2012
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
Product
Errata
65