637
Processor
Does
Not
Report
the
Correct
DRAM
Address
for
MCA
Errors
Within
the
CC
6
Save
Area
Description
While
reporting
an
ECC
machine
check
error
in
the
core
C
6 (
CC
6)
save
area
,
the
processor
may
store
an
internal
address
in
MC
4_
ADDR
(
MSR
0000_0412)
instead
of
the
physical
DRAM
address
.
The
stored
internal
address
can
be
uniquely
identified
,
as
it
matches
000000
FD
_
F
7
xxxxxxh
.
Potential
Effect
on
System
Software
may
not
be
able
to
correctly
interpret
the
machine
check
addresses
for
either
corrected
or
uncorrected
DRAM
errors
.
As
a
result
,
it
may
fail
to
report
the
correct
physical
location
of
the
error
.
Suggested
Workaround
When
using
the
address
in
MC
4_
ADDR
(
MSR
0000_0412)
software
should
compare
MC
4_
ADDR
[47:24]
with
00
FDF
7
h
.
If
it
matches
00
FDF
7
h
,
then
the
following
algorithm
can
be
used
to
correct
the
value
from
MC
4_
ADDR
into
the
physical
DRAM
address
that
is
in
error
.
1.
Software
first
determines
which
node
(
identified
by
its
node
ID
)
reported
the
machine
check
.
This
is
usually
known
to
software
that
reads
MC
4_
ADDR
, (
i
.
e
.
NodeReportingMca
=
CPUID
Fn
8000_001
e
_
ECX
[
NodeId
,
bits
7:0]),
but
in
some
cases
software
may
not
know
the
node
that
reported
the
machine
check
.
In
this
case
,
the
node
that
reported
the
MCA
can
be
determined
as
follows
:
a
.
SourceNode
=
MC
4_
ADDR
[22:20].
In
this
step
,
software
determines
the
node
that
generated
the
CC
6
save
request
.
This
is
not
necessarily
the
node
that
reported
the
machine
check
.
b
.
NodeReportingMca
=
D
(18
h
+
SourceNode
)
F
4
x
128[14:12],
where
"
18
h
+
SourceNode"
is
the
device
number
of
the
node
that
generated
the
CC
6
save
request
.
In
this
step
,
software
accesses
the
C-state
Policy
Control
1
Register
[
CoreStateSaveDestNode
]
on
the
node
that
generated
the
CC
6
save
request
(
SourceNode
from
the
previous
step
).
This
is
the
node
that
reported
the
machine
check
.
2.
DramLimitSysAddrReg
=
D
(18
h
+
NodeReportingMca
)
F
1
x
124,
where
"
18
h
+
NodeReportingMca"
is
the
device
number
of
the
node
that
reported
the
machine
check
.
In
this
step
,
software
reads
the
register
containing
the
DRAM
Limit
System
Address
from
the
node
that
reported
the
machine
check
.
The
register
contents
from
this
step
are
saved
in
a
temporary
variable
for
use
in
later
steps
.
3.
Cc
6
BaseAddress
[47:0] = {
DramLimitSysAddrReg
[20:0], ((
DramLimitSysAddrReg
[23:21]
^
111
b
) << 24),
000000
h
}.
In
this
step
,
software
calculates
the
CC
6
base
address
using
the
DramLimitAddr
.
DramLimitAddr
[47:27]
is
bits
20:0
of
the
register
read
in
step
2.
Bits
26:24
of
the
CC
6
base
address
is
calculated
from
DramInlvEn
.
4.
NodeInterleavingEnabled
= (
DramLimitSysAddrReg
[23:21] != 000
b
).
In
this
step
,
software
determines
if
node
interleaving
is
enabled
.
Node
interleaving
is
enabled
if
the
register
read
in
step
2
has
a
non-zero
value
in
bits
23:21 (
DramIntlvEn
).
5.
If
node
interleaving
is
not
enabled
(!
NodeInterleavingEnabled
from
step
4):
a
.
The
physical
DRAM
address
of
the
machine
check
error
is
(
Cc
6
BaseAddress
+
MC
4_
ADDR
[23:0])
where
Cc
6
BaseAddress
is
the
result
from
step
3.
6.
If
node
interleaving
is
enabled
(
NodeInterleavingEnabled
from
step
4):
a
.
TempMcaAddress
= (
MC
4_
ADDR
[63:0] & 00000000_00
FFF
000
h
) << (
log
(
base
2)
of
(
DramLimitSysAddrReg
[23:21] + 1)).
In
this
step
,
a
temporary
variable
is
initialized
using
the
value
reported
in
MC
4_
ADDR
,
removing
bits
47:24
and
bits
11:0,
and
shifting
the
remaining
bits
by
either
1
(
two
nodes
), 2 (
four
nodes
)
or
3 (
eight
nodes
).
The
node
count
is
indirectly
determined
from
DramIntlvEn
(
bits
23:21
of
the
register
read
in
step
2).
b
.
DramBaseSysAddrReg
=
D
(18
h
+
NodeReportingMca
)
F
1
x
120,
where
"
18
h
+
NodeReportingMca"
is
the
device
number
of
the
node
that
reported
the
machine
check
.
In
this
step
,
software
reads
the
register
48063
Rev
. 3.18
October
2012
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
Product
Errata
47