714
Processor
May
Check
DRAM
Address
Maps
While
Using
L
2
Cache
as
General
Storage
during
Boot
Description
BIOS
accesses
,
while
running
with
L
2
cache
as
general
storage
,
may
hit
in
the
L
2
cache
while
they
are
concurrently
checked
against
the
DRAM
Base
and
Limit
Registers
in
the
northbridge
.
In
the
event
that
this
check
is
performed
while
the
DRAM
address
maps
are
not
yet
completed
by
BIOS
,
the
northbridge
may
flag
a
protocol
error
if
it
cannot
find
a
DRAM
address
map
associated
with
the
BIOS
access
.
AMD
has
only
observed
this
issue
when
node-interleaving
is
enabled
(
DRAM
Base
/
Limit
Register
[
IntlvEn
] (
D
18
F
1
x
[17
C
:140,7
C
:40]
[10:8] != 000
b
).
Potential
Effect
on
System
The
processor
may
recognize
a
northbridge
machine
check
exception
for
a
link
protocol
error
.
The
machine
check
exception
may
cause
a
sync
flood
and
/
or
a
system
reset
.
This
may
be
observed
as
a
system
hang
.
The
machine
check
has
the
following
signature
:
•
The
MC
4_
STAT
register
(
MSR
0000_0411)
is
equal
to
BA
000020_000
B
0
C
0
F
.
Bit
62 (
error
overflow
)
or
bit
59 (
miscellaneous
valid
)
of
MC
4_
STAT
may
or
may
not
be
set
.
•
Bits
5:1
of
the
MC
4_
ADDR
register
(
MSR
0000_0412)
is
equal
to
01001
b
,
indicating
that
a
coherent-only
packet
was
issued
to
a
non-coherent
link
.
The
conditions
under
which
this
erratum
may
be
observed
as
a
system
failure
are
sensitive
to
the
core
and
northbridge
frequencies
.
AMD
has
only
observed
this
erratum
with
one
G
34
processor
configuration
where
the
software
P-state
0
core
frequency
is
less
than
the
northbridge
frequency
.
Suggested
Workaround
BIOS
should
set
MSRC
001_102
A
[8]
to
1
b
prior
to
using
L
2
cache
as
general
storage
during
boot
,
and
then
should
restore
MSRC
001_102
A
[8]
to
it's
original
value
after
completing
L
2
cache
as
general
storage
.
Fix
Planned
No
fix
planned
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
48063
Rev
. 3.18
October
2012
74
Product
Errata