742
DRAM
Scrub
Request
During
Register
Write
May
Cause
Unpredictable
Behavior
Description
The
default
BIOS
sequence
for
enabling
DRAM
scrubbing
and
performing
configuration
accesses
to
enable
DRAM
phy
power
savings
results
in
the
possibility
that
a
DRAM
scrub
event
is
occurring
simultaneously
to
a
BIOS
write
to
a
register
accessed
through
the
DRAM
Controller
Additional
Data
Index
/
Data
port
of
D
18
F
2
x
98_
dct
[1:0]
and
D
18
F
2
x
9
C
_
dct
[1:0].
In
the
event
that
these
operations
occur
at
the
same
time
,
the
processor
DRAM
controller
may
enter
an
invalid
state
.
DRAM
scrubbing
is
enabled
when
the
value
in
Scrub
Rate
Control
Register
[
DramScrub
] (
D
18
F
3
x
58[4:0])
is
not
equal
to
00000
b
or
when
the
DRAM
Scrub
Address
Low
Register
[
ScrubReDirEn
] (
D
18
F
3
x
5
C
[0])
is
equal
to
1
b
.
BIOS
does
not
enable
DRAM
scrubbing
unless
the
DIMMs
support
ECC
.
Potential
Effect
on
System
All
future
reads
of
the
memory
attached
to
the
affected
DRAM
controller
return
unpredictable
data
.
The
processor
may
report
,
but
not
necessarily
in
all
circumstances
,
an
uncorrectable
DRAM
ECC
machine
check
error
.
The
system
may
hang
or
reset
during
the
BIOS
boot
process
,
or
the
inconsistent
memory
data
may
cause
a
system
crash
.
This
failure
is
highly
intermittent
over
multiple
boot
cycles
.
Suggested
Workaround
BIOS
should
complete
all
writes
to
any
register
in
the
range
of
D
18
F
2
x
9
C
_
x
0000_0000_
dct
[1:0]
through
D
18
F
2
x
9
C
_
x
0
D
0
F
_
FFFF
_
dct
[1:0]
prior
to
enabling
DRAM
scrubbing
.
Specifically
,
the
writes
that
are
recommended
by
the
BIOS
and
Kernel
Developer's
Guide
(
BKDG
)
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
,
order
# 42301
section
"DRAM
Phy
Power
Savings"
should
be
performed
earlier
in
the
DCT
initialization
sequence
so
that
they
do
not
occur
while
scrubbing
is
enabled
,
provided
that
they
are
performed
after
completing
DRAM
data
training
.
Fix
Planned
No
fix
planned
48063
Rev
. 3.18
October
2012
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
Product
Errata
87