663
Local
Interrupts
LINT
0/
LINT
1
May
Occur
While
APIC
is
Software
Disabled
Description
The
processor
unmasks
local
interrupts
(
LINT
0
and
LINT
1)
while
the
APIC
is
software
disabled
(
Spurious-
Interrupt
Vector
Register
[
APICSWEn
],
APICF
0[8] = 0
b
).
The
LINT
[1:0]
LVT
entry
mask
bits
(
APIC
3[60:50]
bit
16)
are
cleared
and
cannot
be
set
.
Broadcast
ExtInt
and
NMI
interrupt
requests
can
be
converted
to
LINT
0
and
LINT
1
local
interrupts
respectively
by
setting
Link
Transaction
Control
Register
[
LintEn
] (
D
18
F
0
x
68[16]) = 1
b
.
If
this
bit
is
set
while
the
APIC
is
software
disabled
,
an
ExtInt
or
NMI
interrupt
causes
an
unexpected
local
interrupt
.
Potential
Effect
on
System
Software
may
receive
a
local
interrupt
that
was
not
expected
,
possibly
leading
to
a
system
crash
.
Suggested
Workaround
BIOS
should
set
MSRC
001_001
F
[23] = 1
b
before
enabling
the
APIC
(
APIC
_
BAR
[
ApicEn
]
(
MSR
0000_001
B
[11]) = 1
b
)
or
before
setting
Link
Transaction
Control
[
LintEn
] (
D
18
F
0
x
68[16]) = 1
b
.
Fix
Planned
No
fix
planned
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
48063
Rev
. 3.18
October
2012
54
Product
Errata