719
Instruction-Based
Sampling
Fetch
Counter
Always
Starts
at
Maximum
Value
Description
When
setting
IBS
Fetch
Control
Register
[
IbsFetchEn
] = 1
b
to
enable
IBS
fetch
sampling
,
the
periodic
fetch
counter
always
starts
at
the
maximum
value
programmed
into
IBS
Fetch
Control
Register
[
IbsFetchMaxCnt
]
(
MSRC
001_1030[15:0])
instead
of
starting
at
the
value
written
into
IBS
Fetch
Control
Register
[
IbsFetchCnt
]
(
MSRC
001_1030[19:4]).
Potential
Effect
on
System
System
software
that
is
managing
multiple
processes
or
virtual
machines
with
different
IBS
configurations
may
create
unintended
delays
before
the
next
IBS
sample
by
writing
to
MSRC
001_1030.
In
the
event
that
system
software
consistently
writes
to
MSRC
001_1030,
it
is
possible
that
the
IBS
fetch
counter
never
expires
and
no
instruction
fetches
are
tagged
.
AMD
has
not
observed
this
effect
with
production
software
.
Suggested
Workaround
None
.
Fix
Planned
No
fix
planned
48063
Rev
. 3.18
October
2012
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
Product
Errata
77