•
NBPMCxXXX
[
Y
]:
northbridge
performance
monitor
events
;
XXX
is
the
hexadecimal
event
counter
number
programmed
into
MSRC
001_024[6,4,2,0][
EventSelect
] (
NB
_
PERF
_
CTL
[3:0]
bits
7:0).
Y
,
when
specified
,
signifies
the
unit
mask
programmed
into
MSRC
001_024[6,4,2,0][
UnitMask
] (
NB
_
PERF
_
CTL
[3:0]
bits
15:8).
Many
register
references
use
the
notation
"
[]
"
to
identify
a
range
of
registers
.
For
example
,
D
18
F
2
x
[1,0][4
C
:40]
is
a
shorthand
notation
for
D
18
F
2
x
40,
D
18
F
2
x
44,
D
18
F
2
x
48,
D
18
F
2
x
4
C
,
D
18
F
2
x
140,
D
18
F
2
x
144,
D
18
F
2
x
148,
and
D
18
F
2
x
14
C
.
Arithmetic
and
Logical
Operators
In
this
document
,
formulas
follow
some
Verilog
conventions
as
shown
in
Table
1
.
Table
1.
Arithmetic
and
Logic
Operators
Operator
Definition
{}
Curly
brackets
are
used
to
indicate
a
group
of
bits
that
are
concatenated
together
.
Each
set
of
bits
is
separated
by
a
comma
.
E
.
g
., {
Addr
[3:2],
Xlate
[3:0]}
represents
a
6
-bit
value
;
the
two
MSBs
are
Addr
[3:2]
and
the
four
LSBs
are
Xlate
[3:0].
|
Bitwise
OR
operator
.
E
.
g
. (01
b
| 10
b
== 11
b
).
||
Logical
OR
operator
.
E
.
g
. (01
b
|| 10
b
== 1
b
);
logical
treats
multibit
operand
as
1
if
>=1
and
produces
a
1
-bit
result
.
&
Bitwise
AND
operator
.
E
.
g
. (01
b
& 10
b
== 00
b
).
&&
Logical
AND
operator
.
E
.
g
. (01
b
&& 10
b
== 1
b
);
logical
treats
multibit
operand
as
1
if
>=1
and
produces
a
1
-bit
result
.
^
Bitwise
exclusive-OR
operator
;
sometimes
used
as
"raised
to
the
power
of"
as
well
,
as
indicated
by
the
context
in
which
it
is
used
.
E
.
g
. (01
b
^
10
b
== 11
b
).
E
.
g
. (2
^
2 == 4).
~
Bitwise
NOT
operator
(
also
known
as
one's
complement
).
E
.
g
. (
~
10
b
== 01
b
).
!
Logical
NOT
operator
.
E
.
g
. (!10
b
== 0
b
);
logical
treats
multibit
operand
as
1
if
>=1
and
produces
a
1
-bit
result
.
==
Logical
"is
equal
to"
operator
.
!=
Logical
"is
not
equal
to"
operator
.
<=
Less
than
or
equal
operator
.
>=
Greater
than
or
equal
operator
.
*
Arithmetic
multiplication
operator
.
/
Arithmetic
division
operator
.
<<
Shift
left
first
operand
by
the
number
of
bits
specified
by
the
2
nd
operand
.
E
.
g
. (01
b
<< 01
b
== 10
b
).
>>
Shift
right
first
operand
by
the
number
of
bits
specified
by
the
2
nd
operand
.
E
.
g
. (10
b
>> 01
b
== 01
b
).
Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
48063
Rev
. 3.18
October
2012
8
Conventions